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The spec clarifying for LPC185x.

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by CH Wu on Sun Aug 30 18:44:23 MST 2015
Hello NXP team,

I have few questions regarding the spec description of LPC185x.
I want NXP member feedback me these questions because that are very important to us.

1.There are many descriptions in the user manual as following but didn’t descript the “O”. What is the “O” meaning for reset state of GPIO?
[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in the SFS register to enable the input buffer; I = input; OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset without boot code operation.
2.The reset state was descripted in user manual for GPIO status indication. Does the “Reset state” mean the reset pin keeping at low?
3.What is the meaning for normal drive strength & high drive strength?
I captured the following description from UM10430 for question 3.
[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength.
[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels, and hysteresis; high drive strength.
4.The P3_2 is “OL” during “Reset state” descripted in UM10430. What are the configurations of I/O pas? I referred to the block diagram of the I/O pad but I can’t figure out the configurations.
Please refer to the Fig. 34. Block diagram of the I/O pad of UM10430.

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