LPC1850 - Determining cause of last reset

[lpcware]

Content originally posted in LPCWare by surrealist14 on Fri Aug 09 14:06:50 MST 2013
Many processors have a status register that allows a programmer to determine the cause of the last reset.  In my case, I'm using an LPC1850.  The diagram in the users manual shows that the potential sources for a CORE_RST are:

* _RESET
* _POR
* BOD reset
* WWDT reset
* PMC reset

Can anyone provide an example of some code that determines the cause of the last reset on the LPC18XX?  According to an apps engineer at NXP, we shouldn't use the RGU for this purpose, because a core reset will cause the RGU block itself to be reset, and all of its values will be set to default values.

Thanks for any/all help!

[javiervallori]

I knew it was a very long long long time ago question. But it hasn't  been answered yet, and I'm also interested about it. Any suggestions?

[lpcware]

Content originally posted in LPCWare by Cusko on Wed Sep 03 04:34:40 MST 2014
I am also interested about this.
I try to find out a way to know if a watchdog reset occurred. According to the user manual there should be the flag WDTOF in the Watchdog Mode register (MOD - 0x4008 0000). This flag should be set if a watchdog times out and should not be cleared if watchdog resets. But the flag WDTOF is clear even if a WD resets the core. Why and how to detect the WD reset after core reset?

[lpcware]

Content originally posted in LPCWare by lifejoker on Mon Aug 18 22:04:38 MST 2014
I knew it was a long time ago question. but I met the same problem, is there any way to determine the cause of last reset?

Thanks~