lpcware

EMC problem

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by BlackJack on Tue Mar 04 02:21:45 MST 2014
Dear all,

currently I am working on a project with the LPC1837 microcontroller. Now I have a problem with the EMC (External Memory Controller). I am using the EMC only for a static 8bit memory access and in principle the EMC is working well, but there is one weird behaviour. In the debug mode the read and write accesses are working as defined, but out of the debug mode the EMC will create a lot of read accesses. Unfortunately, I have no idea why the EMC is creating all the read accesses even though the memory access already finished.

For better understanding I have attached two pictures which I have made by an oscilloscope. On these pictures you can see three signals (#CS, #RD, #WR). The picture F0019TEK.jpg I have made in the debug mode. The second picture F0018TEK.jpg I have made out of the debug mode.

One more short information regarding the initialisation of the EMC. I have disabled the EMC buffer, because I do not know how I can use the DATAIN FIFO of the EMC. Unfortunately, regarding this topic the UM10430 is not clear enough for me.

Here is my initialisation procedure for the EMC:

uint32_t div = 0u;
uint32_t n;

LPC_CREG->CREG6 |= (1 << 16);  // EMC_CLK_DIV divided by 2
LPC_CCU1->CLK_M3_EMCDIV_CFG = (1 << 0) | // RUN: Clock is enabled
                               (1 << 1) | // AUTO: Auto is enabled
(1 << 5);  // DIV: Clock divider value is 2

  /* Select and enable EMC branch clock */
//  LPC_CCU1->CLK_M3_EMC_CFG = (1 << 2) | (1 << 1) | 1;
//  while (!(LPC_CCU1->CLK_M3_EMC_STAT & 1));

  /* Konfiguration der EMC Portpins */
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */

  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  #RD                          */
  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  #CS0                         */
  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  #WR                          */

// Datenleitungen
  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */

  // Adressleitungen
  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */

  LPC_EMC->CONTROL  =  0x00000001;       /* EMC Enable                        */
LPC_EMC->STATICCONFIG0 = (1 << 7);     /* Byte lane state: use WE signal    */


  /* Configure EMC clock-out pins                                             */
  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */

  /* Set Static Memory Write Delay to 200ns                 */
  //LPC_EMC->STATICWAITWR0 = 1 + EMC_NANOSEC(200, SystemCoreClock, div);
  LPC_EMC->STATICWAITWR0 = 0x14; // WAITWR: Delay from CS to write access
LPC_EMC->STATICWAITWEN0 = 0x3; // WAITWEN: Delay from CS to write enable


  /* Set Static Memory Read Delay to 200ns                 */
  //LPC_EMC->STATICWAITRD0  = 1 + EMC_NANOSEC(200, SystemCoreClock, div);
LPC_EMC->STATICWAITRD0 = 0x14; // WAITOE: Delay from CS to read access
LPC_EMC->STATICWAITOEN0 = 0x3;


  LPC_EMC->STATICCONFIG0 &= ~(1 << 19) ; /* Disable buffer                      */


May somebody can give me important information concerning my problem.

I am really grateful for every idea and feedback. Thank you!

Best regards

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