A board implemented with LPC1850 has DEBUG and clock problems

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by MKai on Tue May 27 06:17:34 MST 2014
  I have implemented a board with LPC1850, Now, I have soldered the following components ob the board:
    (1) 30 filter capacitor of 0.1uF.
    (2) The pull-up resistor of DEBUG Enable pin.
    (3) The switch of #ISP pin.
    (4) The switch of P2_9, P2_8, P1_2, P1_1.
    (5) The interface of JTAG.
    (6) A 32.768KHz oscillator to RTCX1 and RTCX2 matching capacitor.
    (7) A 12MHz oscillator to XTAL1 and XTAL2 matching capacitor.
  I have a main board with power module and other devices, and I could make sure the power module work well.
  Now, I just want to use the on-chip RAM to do some debug. So I haven't soldered other chips.
  Case 1: When I pull the #ISP pin high and pull the pins of P2_9, P2_8, P1_2, P1_1 high, and the board power up, I test the CLK1 pin using  oscilloscope, getting wave of 16~20MHz with some noice. In this case, I connect the board to a PC through ULINK2, and when I open debug in Keil, it will info me "SWD Communication Failed".
  Case 2: Then, I pull the #ISP pin low and keep others. I test the CLK1 pin, getting wave of 67~68MHz. When I open debug in Keil, it could connect successfully. But many registers could not be read("Connot access memory") and written.
  I'm not sure that the two oscillators start successfully, and I wonder if it has some influence to debug when start fails. After reading the user manual, I think the CLK1 pin should has 12MHz output in Case 1 and 96MHz in Case 2. What could cause the abnormal clock output? Could someone analyse my case and give me some help?
  Many thanks!