lpcware

GPIO DMA Again

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on May 22, 2017 by Kaiyue WANG
Content originally posted in LPCWare by dsidlauskas on Tue Apr 01 18:11:00 MST 2014
I need some help, please.

I have read in the manual and a number of other places that the DMA controller must be programmed for memory to memory transfers to DMA from/to GPIO.
However, in the code for NXP's app note AN11365 the DMA  channel configuration is set for peripheral to memory to do GPIO to memory transfers

Here's NXP's code::
s_ccb.pCHN->CONFIG = | XferDoneIrqEn | 0UL<<0  | YACB_SCTDMAPERIPNUM<<1 | 0UL<<6 | 2UL<<11 | 1UL<<15;
the 2UL<<11 bits are what's setting up the p>m transfer, and is documented as such in the codes comments.

Can someone please clarify this for me, please.

What I'm trying to do use Timer3 Capture 1 to trigger a DMA request which would result in a DMA transfer from GPIO to memory.
Timer 3 is set as a counter and  set to reset and toggle it's match bit on a match. The match value is a 1.
DMA is configured for m>m, with source address = GPIO port address and destination of external RAM.
LPC->CREG = 3 sets the DMA request from T3C1 to peripheral 0.
The DMA channel reg is configured for peripheral 0 as it's source.

So whats my problem?

Well, when I run it it DMA's from GPIO to memory just fine. However, it completely ignores the DMA requests from Timer3 and completes the full DMA in about 1/10th of the time it should, so I assume it's running on it's internal clock for DMA requests.

I appreciate any help.

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