lpcware

Is this SDRAM compatible with 18xx ?

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by chris.bayley on Thu Jun 18 18:35:16 MST 2015
I am working with a form factor preproduction prototype PCB fitted with an LPC1837 and an ISSI SDRAM (IS42SM16200D) which is a 1M x 16bit x 2banks device.
From it's data sheet:
In general, this 32Mb SDRAM (1M x 16Bits x 2banks) is a dual-bank DRAM that operates at 3.0V/3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 512 columns by 16-bits


I am becoming increasingly concerned that the EMC addressing modes of the 18xx may not support the Row/Column layout of this device:

From Table 365 of UM10430:
[img]http://www.lpcware.com/system/files/images/Screen%20Shot%202015-06-19%20at%201.10.46%20pm.png[/img]

So my SDRAM is 32Mb (1M x 16 x 2) and according to its data sheet it is laid out as:
2048 rows x 512 columns x 2 banks x 16bit
hence the row addressing is on A0-A10 and the col on A0-A8.

I cannot see any address mapping mode in Table 365 that indicates support for this configuration, are we up a creek or is there some mapping that will yield full access to the memory ???

I have tried all the given options support 2 banks but have not established a usable result.

Cheers all,
Chris

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