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Bus Faults with setting LCD Display TFT

‎06-15-2016 11:21 AM
941 Views
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Weizhong-YANG on Fri May 27 06:50:19 MST 2016
Hi sirs,

We are working on new design about CPU card which include core cortex M3 LPC1850FET180. We meet a problem.
Description of ours system
THE CPU is  composed of :
1 Microcontrôler : LPC1850FET180
1 Spifi flash : S25FL032P (4 M) (code)
1 SDRAM : MT48LC4M16A2P_6A (8 M)
1 Flash parallel 32Mb: SST39VF3201B-70
Driving of display LCD TFT 5,7” (640 X 480)
Display memory LCD 0x28000000-0x2812C000 (SDRAM)
Graphics library emWin SEGGER V.524
Option for File GUIConf.c :
Memory Assignment :
Code/Const : default
Zero Initialized Data : RAM2[0x2812D000-0x283FFFFF] (SDRAM)
Other Data: RAM2[0x2812D000-0x283FFFFF] (SDRAM)
               
Encountered problem:
It’s occurs when we set a program for driving display.
(However, a testing program of the SDRAM in writing and reading on 8bits, 16bits et 32 bits works without fault)
program is blocked in the proceedings GUI_Init() (emWin SEGGER)
which jumps to « BusFault_Handler » with Bus Faults : IMPRECISERR.

If we set GUIConf.c to the RAM :
   Option for File GUIConf.c :
Memory Assignment :
Code/Const : default
Zero Initialized Data : IRAM2 [0x20000000-0x2000FFFF]
Other Data: IRAM2 [0x20000000-0x2000FFFF]

GUI_Init() works without problem.
But with fonctions GUI_SetBkColor(GUI_RED);
GUI_Clear();
GUI_Delay(1000);
We get:  Bus Faults : PRECISERR, BFARVALID,
BUS_FAULT_ADDR: 0x1A7F4A7C/ 0x000002DF/ 0xB0022F34/……,
BUS_FAULT_STAT: 0x82

We use the following tools
Infos sur MDK Microcontroller Development Kit : µVision 5 :
IDE-Version:
µVision V5.14.0.0
Copyright (C) 2015 ARM Ltd and ARM Germany GmbH. All rights reserved.

Tool Version Numbers:
Toolchain:        MDK-ARM Professional  Version: 5.14.0.0
Toolchain Path:    C:\Keil\ARM\ARMCC\Bin
C Compiler:         Armcc.exe        V5.05 update 1 (build 106)
Assembler:          Armasm.exe        V5.05 update 1 (build 106)
Linker/Locator:     ArmLink.exe        V5.05 update 1 (build 106)
Library Manager:    ArmAr.exe        V5.05 update 1 (build 106)
Hex Converter:      FromElf.exe        V5.05 update 1 (build 106)
CPU DLL:               SARMCM3.DLL          V5.14.0.0
Dialog DLL:         DCM.DLL              V1.13.1.0
Target DLL:             UL2CM3.DLL           V1.155.0.0
Dialog DLL:         TCM.DLL              V1.14.4.0

Debug avec ULINK2 KEIL

Nota:
We have controled on the electronic board that we haven’t short-circuit between datas, adress, no cutted tracks
With scopemeter, signals seem corrects…

Could you help us ? ?

Thank you in advance.
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‎06-18-2016 06:11 PM
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lpcware
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‎06-15-2016 11:21 AM
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Weizhong-YANG on Thu Jun 02 07:50:47 MST 2016
Hello bavarian

thank you for your reply.
I have got to change PPL1 to 120 MHz(FCLKOUT) and and 60MHz for the EMC ,
Debug with ULINK2 KEIL : sometmes I have
Usage Faults:
USG_FAULT_STAT: 0x0100, UNALIGNED
But the soft work very good without ULINK2 (debug)?

I think supply of the CPU is not involved.
we use a power labo.

Micro SDRAM MT48LC4M16A2P_6A (4 Meg x 16 (1 Meg x 16 x 4 banks)) setting:
/*----------------------------------------------------------------------------
  Initialize external memory controller
*----------------------------------------------------------------------------*/

void SystemInit_ExtMemCtl (void) {
  uint32_t emcdivby2_buf[emcdivby2_szw];
  uint32_t div, n;

  /* Select and enable EMC branch clock */
  LPC_CCU1->CLK_M3_EMC_CFG = (1 << 2) | (1 << 1) | 1;
  while (!(LPC_CCU1->CLK_M3_EMC_STAT & 1));

  /* Set EMC clock output delay */ 
  if (SystemCoreClock < 80000000UL) {
    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay       */
  }
  else {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay   */
}

  /* Configure EMC port pins */
  LPC_SCU->SFSP1_0  = EMC_PIN_SET | 2;  /* P1_0:  A5                          */
  LPC_SCU->SFSP1_1  = EMC_PIN_SET | 2;  /* P1_1:  A6                          */
  LPC_SCU->SFSP1_2  = EMC_PIN_SET | 2;  /* P1_2:  A7                          */
  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  OE                          */
  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  CS0                         */
  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  WE                          */
  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */

  LPC_SCU->SFSP2_0  = EMC_PIN_SET | 2;  /* P2_0:  A13                         */
  LPC_SCU->SFSP2_1  = EMC_PIN_SET | 2;  /* P2_1:  A12                         */
  LPC_SCU->SFSP2_2  = EMC_PIN_SET | 2;  /* P2_2:  A11                         */
  LPC_SCU->SFSP2_6  = EMC_PIN_SET | 2;  /* P2_6:  A10                         */
  LPC_SCU->SFSP2_7  = EMC_PIN_SET | 3;  /* P2_7:  A9                          */
  LPC_SCU->SFSP2_8  = EMC_PIN_SET | 3;  /* P2_8:  A8                          */
  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */
  LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3;  /* P2_13: A4                          */

  LPC_SCU->SFSP5_0  = EMC_PIN_SET | 2;  /* P5_0:  D12                         */
  LPC_SCU->SFSP5_1  = EMC_PIN_SET | 2;  /* P5_1:  D13                         */
  LPC_SCU->SFSP5_2  = EMC_PIN_SET | 2;  /* P5_2:  D14                         */
  LPC_SCU->SFSP5_3  = EMC_PIN_SET | 2;  /* P5_3:  D15                         */
  LPC_SCU->SFSP5_4  = EMC_PIN_SET | 2;  /* P5_4:  D8                          */
  LPC_SCU->SFSP5_5  = EMC_PIN_SET | 2;  /* P5_5:  D9                          */
  LPC_SCU->SFSP5_6  = EMC_PIN_SET | 2;  /* P5_6:  D10                         */
  LPC_SCU->SFSP5_7  = EMC_PIN_SET | 2;  /* P5_7:  D11                         */
  LPC_SCU->SFSP6_4  = EMC_PIN_SET | 3;  /* P6_4:  CAS                         */
  LPC_SCU->SFSP6_5  = EMC_PIN_SET | 3;  /* P6_5:  RAS                         */
  LPC_SCU->SFSP6_7  = EMC_PIN_SET | 1;  /* P6_7:  A15                         */
  LPC_SCU->SFSP6_8  = EMC_PIN_SET | 1;  /* P6_8:  A14                         */
  LPC_SCU->SFSP6_9  = EMC_PIN_SET | 3;  /* P6_9:  DYCS0                       */
  LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3;  /* P6_10: DQMOUT1                     */
  LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3;  /* P6_11: CKEOUT0                     */
  LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3;  /* P6_12: DQMOUT0                     */

  LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2;  /* PD_15: A17                         */
  LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2;  /* PD_16: A16                         */

  LPC_SCU->SFSPE_0  = EMC_PIN_SET | 3;  /* PE_0:  A18                         */
  LPC_SCU->SFSPE_1  = EMC_PIN_SET | 3;  /* PE_1:  A19                         */
  LPC_SCU->SFSPE_2  = EMC_PIN_SET | 3;  /* PE_2:  A20                         */
  LPC_SCU->SFSPE_3  = EMC_PIN_SET | 3;  /* PE_3:  A21                         */
  LPC_SCU->SFSPE_4  = EMC_PIN_SET | 3;  /* PE_4:  A22                         */

  LPC_EMC->CONTROL  = 0x00000001;       /* EMC Enable                         */
  LPC_EMC->CONFIG   = 0x00000000;       /* Little-endian, Clock Ratio 1:1     */

  div = 0;
  if (SystemCoreClock > 120000000UL) {
    /* Use EMC clock divider and EMC clock output delay */
    div = 1;
    /* Following code must be executed in RAM to ensure stable operation      */
    /* LPC_CCU1->CLK_M3_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
    /* while (!(LPC_CCU1->CLK_M3_EMCDIV_STAT & 1));                           */

    /* This code configures EMC clock divider and is executed in RAM          */
    for (n = 0; n < emcdivby2_szw; n++) {
      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
    }
    __ISB();
    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M3_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
    for (n = 0; n < emcdivby2_szw; n++) {
      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
    }
  }

  /* Configure EMC clock-out pins                                             */
  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */
 
  /* Static memory configuration (chip select 0)                              */
#if (USE_EXT_STAT_MEM_CS0)
LPC_EMC->STATICCONFIG0 = 0x81;//14/01/2016
  LPC_EMC->STATICWAITOEN0 = (1 <<  0) ; /* Wait output enable: No delay - 1    */
 
  LPC_EMC->STATICWAITPAG0 = 1;

  /* Set Static Memory Read Delay for 90ns External NOR Flash                 */
LPC_EMC->STATICWAITRD0 = 0x06;

#endif
 
  /* Dynamic memory configuration (chip select 0)                             */
#if (USE_EXT_DYN_MEM_CS0)

  /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
  LPC_EMC->DYNAMICCONFIG0    = (0 << 14) |  /* AM[14]   = 0                   */
                               (0 << 12) |  /* AM[12]   = 0                   */
                               (1 <<  9) |  /* AM[11:9] = 1                   */
                               (1 <<  7) ;  /* AM[8:7]  = 1                   */

  LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
  LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK   */

  LPC_EMC->DYNAMICRP         = EMC_NANOSEC (20, SystemCoreClock, div);
  LPC_EMC->DYNAMICRAS        = EMC_NANOSEC (42, SystemCoreClock, div);
  LPC_EMC->DYNAMICSREX       = EMC_NANOSEC (63, SystemCoreClock, div);
  LPC_EMC->DYNAMICAPR        = EMC_NANOSEC (70, SystemCoreClock, div);//5
  LPC_EMC->DYNAMICDAL        = EMC_NANOSEC (70, SystemCoreClock, div);//5
  LPC_EMC->DYNAMICWR         = EMC_NANOSEC (30, SystemCoreClock, div);//2
  LPC_EMC->DYNAMICRC         = EMC_NANOSEC (63, SystemCoreClock, div);
  LPC_EMC->DYNAMICRFC        = EMC_NANOSEC (63, SystemCoreClock, div);
  LPC_EMC->DYNAMICXSR        = EMC_NANOSEC (63, SystemCoreClock, div);
  LPC_EMC->DYNAMICRRD        = EMC_NANOSEC (14, SystemCoreClock, div);
  LPC_EMC->DYNAMICMRD        = EMC_NANOSEC (30, SystemCoreClock, div);//2

  WaitUs (100);
  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
  WaitUs (10);
  LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
  WaitUs (1);
  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
  WaitUs (1);
  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
  WaitUs (10);
  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
  WaitUs (10);
  LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */

  /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
  WR_MODE(((3 << 4) | 3) << 11);//For a single 16-bit external SDRAM chip set the burst length to 8.
  WaitUs (10);
  LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */
  LPC_EMC->DYNAMICCONFIG0   |= (1 << 19);   /* Enable buffer                  */
#endif
}

Could you help us ?

Thank you in advance
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‎06-15-2016 11:21 AM
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by bavarian on Wed Jun 01 06:23:40 MST 2016
The error message tells me that you use the software for the MCB1800 board, coming along with the Keil IDE.
There's in principle nothing against it, however, I recommend also a look at the LPCOpen package, which includes a lot of examples which can be useful as starting point for an own development.

The easiest check with a lower frequency is with 72 MHz, then you only need to change a minimum in the code. At this speed you should have excluded all possibilities to run into problem because of a bad board design or a weak power supply structure.The correct PLL1 settings for 72MHz CPU and EMC frequency is shown below:

 *----------------------------------------------------------------------------
 * PLL1 requirements:
 * | Frequency |  Minimum  |  Maximum  |               Note                   |
 * |  FCLKIN   |    1MHz   |   25MHz   |   Clock source is external crystal   |
 * |  FCLKIN   |    1MHz   |   50MHz   |                                      |
 * |   FCCO    |  156MHz   |  320MHz   |                                      |
 * |  FCLKOUT  | 9.75MHz   |  320MHz   |                                      |
 *----------------------------------------------------------------------------
 * Configuration examples:
 * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECT | FBSEL | BYPASS |
 * |  36MHz | 288MHz |  1  |  24 |  4  |   0    |   0   |    0   |
 * |  72MHz | 288MHz |  1  |  24 |  2  |   0    |   0   |    0   |  <========
 * | 100MHz | 200MHz |  3  |  50 |  1  |   0    |   0   |    0   |
 * | 120MHz | 240MHz |  1  |  20 |  1  |   0    |   0   |    0   | 
 * | 160MHz | 160MHz |  3  |  40 |  x  |   1    |   0   |    0   |
 * | 180MHz | 180MHz |  1  |  15 |  x  |   1    |   0   |    0   |
 *----------------------------------------------------------------------------
 * Relations beetwen PLL dividers and definitions:
 * N = PLL1_NSEL + 1,     M = PLL1_MSEL + 1,     P = 2 ^ PLL1_PSEL
 *----------------------------------------------------------------------------*/

/* PLL1 output clock: 72 MHz                                                  */
#define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
#define PLL1_MSEL  23           /* Range [0 - 255]: Feedback-divider ratio M  */
#define PLL1_PSEL   1           /* Range [0 -   3]: Post-divider ratio P      */

#define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
#define PLL1_DIRECT 0           /* 0: Use PSEL, 1: Don't use PSEL             */
#define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
                                /* 1: FCLKOUT is used as PLL feedback         */



If your test is based on this code from Keil, then you also need to consider the differences between the MCB1800 board hardware and your own board.
One significant difference is the SDRAM bus width. The board from Keil uses a 32-bit SDRAM Micron 48LC4M32, you have a 16-bit.

/* This is the settings for the 32-bit SDRAM on the Keil MCB1800 board        */
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8   */
  LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
                               (0 << 12) |  /* AM[12]   = 0                   */
                               (2 <<  9) |  /* AM[11:9] = 2                   */
                               (2 <<  7) ;  /* AM[8:7]  = 2                   */
  :
  :
  :

/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3     */
  WR_MODE(((3 << 4) | 2) << 12);


You have to adapt this to a 16-bit configuration. Look into the user manual of the LPC1800 for the correct settings of DYNAMICCONFIG0 and the correct value for writing to the mode register (WR_MODE macro).
The other settings can stay the same, this should work.

Regards,
NXP Support Team.


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‎06-15-2016 11:21 AM
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Weizhong-YANG on Wed Jun 01 05:18:36 MST 2016
Hello bavarian

thank you for your reply.
I try to change PPL1 to 120 MHz,
But I have error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)" ?
How can i decrease the SDRAM bus speed: 120MHz CPU and 60MHz for the EMC ?


Could you help us ? ?

Thank you in advance.

Wzh-Y
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‎06-15-2016 11:21 AM
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by bavarian on Tue May 31 05:48:39 MST 2016
The first step here should be a detailed check of the SDRAM bus functionality.
You say that you run an SDRAM test software successfully, but this could mean that with your test you just can't see the error.
Please decrease the SDRAM bus speed to e.g. 60MHz (120MHz CPU and 60MHz for the EMC or 60MHz for CPU and EMC) in order to check if there is a timing issue. Timing issues can be a consequence of a weak power supply structure, a bad PCB design or incorrect register settings.
The bus fault could mean that an internal timing of the EMC i/f is bad, this can either come from a weak power structure or a wrong register setting (or both ;-)

Regards,
NXP Support Team
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