LPC18xx EMC with synchronous interface to an FPGA

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by devel@latke.net on Wed Aug 07 12:39:28 MST 2013
I am in the process of choosing an ARM device for a project which requires High Speed USB and also includes an FPGA. LPC18xx looks promising.

Can the EMC be used as a synchronous bus interface to my FPGA? I see that there is a note in the data sheet about "Synchronous static memory devices (synchronous burst mode) are not supported." I don't need a burst mode.

I guess my questions are when the EMC is configured to work as a static external memory interface, with accesses in one of the four static-memory chip select address ranges:

Can I use one of the EMC_CLK signals for my FPGA clock, or are they only available if a dynamic interface is enabled?

If so, then are the various EMC signals (EMC_A[], EMC_WE, EMC_OE, EMC_CS, EMC_D) synchronous to that clock?

Thanks in advance.