LPC 1857 SSP0 issue when using P1_1 as MISO

[lpcware]

Content originally posted in LPCWare by Manikandan_108 on Thu May 05 01:59:06 MST 2016
Hi NXP support team,

I am using Keil MCB1857 Evaluation Board and i have configured SSP0 as below:

P3_0 => clock
P1_0 => CS
P1_1 => MISO
P1_2 => MOSI

configured as SSP_MODE_MASTER,SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA1_CPOL0, speed 3 MHZ.


Issue:
As a master SSP0 writes data in the bus which is correctly received at the slave end hence, no issue on the MOSI but, when reads data from the slave, data is always 0xFF. Upon probing the MISO line on a CRO, data comes properly on the CRO but, data register always reads 0xFF. When i used a different pin[PF_2] for MISO then, the data register is reading the correct values.

Chip_SCU_PinMuxSet(0xf, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)); => Working case
Chip_SCU_PinMuxSet(0x1, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC5 )); => Not working case

Since P1_1 is also a boot status pin, I tried both high and low of the P1_1 on board jumper but didn't help, Any special configuration is required to use P1_1 as MISO for SSP0 ?

Thanks,
Manikandan.

[lpcware]

bump

[lpcware]

Content originally posted in LPCWare by lpcmunich on Thu May 19 07:29:27 MST 2016
Hi Manikandan,
When you are using P1_1 as SSP0_MISO, you should not tie it to HIGH or LOW.
So just remove the on-board boot status jumper completely and test it.
One more thing, on Keil MCB1857 board P1_1 is also connected to the external memories.
And this might affect SSP/SPI functionality, so you should try isolating these connections if you are not using these external memories.
But considering the effort/complexity, I would suggest you to use PF_2 or any other pin for SSP0_MISO function.