LPC1857 NVIC Priority Registers

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by SteveO on Wed Apr 15 16:49:49 MST 2015
Having difficulty figuring out the NVIC interrupt priority registers on the LPC1857.  I'm not using CMSIS or other library code.

The LPC1857 User Manual (rev 2.6) says the NVIC supports 53 vectored interrupts.  Table 73 shows eight priority registers (IPR0-IPR7).  According to Table 73, "Each register contains the 3-bit priority fields for 4 interrupts."  8 * 4 = 32, which is less than the 53 interrupts supported by the chip.

I peeked at CMSIS and other library code, and it looks like there are really more than 8 NVIC IPR registers.   I think there are really registers IPR0-IPR13 and the datasheet is wrong where it says there is only IPR0-IPR7.  Can anyone confirm this?