lpcware

SDRAM bank interleave

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by tvink on Tue Feb 24 06:49:34 MST 2015
Hi,

I am using a 64Mbit SDRAM that has 12 bit ROW addressing, 8 bit COL addressing, and it has 4 banks.

I am wondering what is the best way to connect the SDRAM's Bank address pins to the LPC1837. 

Also wondering what I should choose for address mapping in the LPC1837 "Dynamic Memory Configuration" registers.  I think my two choices area
1) 64Mb ( Row, Bank, Column )
or
2) 64Mb ( Bank, Row, column )


It seems that the 1st choice would promote interleaving... but does the EMC take care of that no matter which choice I make?

Does this choice affect the way the bank selects are wired to the LPC1837?

How should the bank selects be wired to the LPC1837 and which address mapping should I choose?


Thanks,
Tony

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