LPC1857 C_CAN0 Interrupt problem

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Yannick.C on Tue Feb 24 05:26:54 MST 2015
Dear All,

When an interruption is triggered on C_CAN0 the program go to Hardfault handler. If I disable interrupts of the C_CAN0, it seems to work correctly.
If I change controller to C_CAN1, interrupt occurs without any troubles.

In UM10430 rev2.6 I think there is an error on Table 72 (NVIC interrupt sources). All vector offset are wrong (and overlap with previous) from the interrupt ID 37 (GPIO pin interrupt 5). I think offset for C_CAN0 is 0x10C instead of 0xFC. But the default startup.s do not have this problem so it's just a datasheet error.
I think the real problem is that C_CAN0 handler address is read from address 0x0C instead of 0x10C, 0x0C is the offset of Hardfault.

I have a LPC1857JET256 with a -Y revision (normally engeineering sample of the Rev A).

I really need to use interrupt and C_CAN0, is someone has encountered the same problem ?

Best regards,