lpcware

Can I use SDR CLK1 instead of SDR CLK0 for 128Mb x16 single-chip SDRAM?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by darkknight on Mon Jul 16 08:54:28 MST 2012
Hello All,

I have a question regarding the LPC1830 SDRAM interface. As you know very well, there are four possible SDRAM clock pins (CLK0 - CLK3). I have a single-chip 128Mb x16 SDRAM in my design. Initially, I was thinking about bringing EMC_CLK0 (SDRAM clock 0) from the processor to the SDRAM. However, I noticed that, if I assign CLK1 (SDRAM clock 1) as my SDRAM clock, the layout will be easier and I will not have to use any vias on that clock signal. That's because CLK1 pin is T10, which is an edge pin on the BGA. Also, if I can use CLK1 as the SDRAM clock, do I have to then use CKE1 instead of CKE0 for clock enable pin? Basically, if I use the following signals for the SDRAM interface, will there be any issue?

CLK1 - SDRAM clock
EMC_CKEOUT0 - SDRAM clock enable 0
EMC_DYCS0 - SDRAM chip select 0

Thank you for your help.



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