LPC 1857 SSP MISO behavior

[lpcware]

Content originally posted in LPCWare by Manikandan_108 on Wed Mar 02 04:21:55 MST 2016
Hi NXP support team,

I am using Keil developed LPC 1857 evaluation board.
I configured ssp1 as master for 8 bits, spi frame format, clock phase=1, clock polarity=0.
i have a spi slave which can work upto 20 Mhz and is configured as mentioned above to write a value 0x0A when clock is provided by the master.
I get the data as 0x0A correctly in MISO when master is configured for 200Khz speed.
I get 0x05 as data in MISO sometimes when the speed is 13Mhz.
i get 0x05 as data in MISO always when the speed is 20 Mhz.

From the CRO i could see the MISO data is getting delayed by ~20ns. Is this an issue with master ? if so, how to solve this ? please comment.
Attaching the CRO waveforms for reference.

Thanks,
Manikandan.

[lpcware]

bump

[lpcware]

Content originally posted in LPCWare by Manikandan_108 on Thu Mar 03 05:13:11 MST 2016
channel_0 is clock
channel_2 is MOSI
channel_3 is MISO
channel_1 is chip select

i have set clock and chip select pin in the SCU as ( Disable pull-down and pull-up resistor at resistor at pad,Enable high-speed slew,Enable Input buffer,Disable input glitch filter).
i have set mosi and miso in the SCU as (Disable pull-down and pull-up resistor at resistor at pad,Enable Input buffer,Disable input glitch filter).

I am using 5 single core wires of length ~20 cms.
i will try with shorter wires.

[lpcware]

Content originally posted in LPCWare by starblue on Thu Mar 03 02:15:16 MST 2016
You don't mention what the two data traces in your images are, but I guess the third signal is MISO. It seems to be too slow so that there is not enough setup time before the falling edge of the clock.
When you have signal problems, you should look at it with an oscilloscope, not a logic analyzer.
You don't mention how you set up the clock and MISO pin in the system control unit. Try setting clock to fast slew rate and disable input glitch filter on MISO.

Maybe your wires are too long or form a too big loop, so that signals are slowed down. Try to make them short as possible and put the signal close to ground (use twisted pair if these are loose wires).

[lpcware]

Content originally posted in LPCWare by Manikandan_108 on Wed Mar 02 22:37:54 MST 2016
Serial Clock Rate = PCLK / (CPSDVSR x [SCR+1])

CPSDVSR = 2;
SCR = 4;

and i see 17.86 Mhz in the CRO as the clock speed hence, PCLK should be ~ 180 Mhz.

[lpcware]

Content originally posted in LPCWare by Manikandan_108 on Wed Mar 02 06:28:16 MST 2016
No it is 180 Mhz only.

[lpcware]

Content originally posted in LPCWare by starblue on Wed Mar 02 05:40:09 MST 2016
According to the latest data sheet (2015-11-17) LPC1857 has a maximal clock frequency of 180 MHz, are you overclocking it?

[lpcware]

Content originally posted in LPCWare by Manikandan_108 on Wed Mar 02 05:21:40 MST 2016
Yes, it is exactly 17.86 Mhz. I use <Chip_SSP_SetBitRate> function to set the speed.

[lpcware]

Content originally posted in LPCWare by mysepp on Wed Mar 02 05:10:00 MST 2016
BTW: How do you get 20 MHz? 204 MHz / 12 = 17 MHz. Or do you use different clock than 204 MHz?

[lpcware]

Content originally posted in LPCWare by mysepp on Wed Mar 02 05:07:40 MST 2016
Check latest data sheet
(if not as up-to-date as LPC4357, perhaps you can get hints from LPC4357 data sheet).
Check if maximum possible (via registers) is also maximum supported (in data sheet).