LPC 1857 SSP MISO behavior

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by Manikandan_108 on Wed Mar 02 04:21:55 MST 2016
Hi NXP support team,

I am using Keil developed LPC 1857 evaluation board.
I configured ssp1 as master for 8 bits, spi frame format, clock phase=1, clock polarity=0.
i have a spi slave which can work upto 20 Mhz and is configured as mentioned above to write a value 0x0A when clock is provided by the master.
I get the data as 0x0A correctly in MISO when master is configured for 200Khz speed.
I get 0x05 as data in MISO sometimes when the speed is 13Mhz.
i get 0x05 as data in MISO always when the speed is 20 Mhz.

From the CRO i could see the MISO data is getting delayed by ~20ns. Is this an issue with master ? if so, how to solve this ? please comment.
Attaching the CRO waveforms for reference.