lpcware

Disable interrupt tail-chaining

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by fruitmans on Mon Oct 27 02:36:00 MST 2014
Hello there,

I am using the LPC1812 within my project and have a question about the interrupt tail-chaining mechanism. I need to generate a short output pusle on a pin with a defined length of several clock cycles. I am using a external match pin that set the output on match and want to reset the output in the interrupt service routine of the timer match. Normally it takes 12 clock cycles to enter the ISR but when the interrupt is tail-chained it only takes 6 cycles. In most of the situations this is desired but in my situation it will shorten the pulse with approximately 25% and i cannot afford this variation. Is there a way to disable the tail-chaining mechanism or is there a way to detect that the interrupt call was handled with tail chaining on another active ISR?

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