PWM can't be set to 0% duty cycle

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by giusloq on Fri Apr 17 02:06:40 MST 2015
I'm able to configure and use the PWM output with whatever duty cycle, except 0%, i.e. setting the output always low.

In datasheet (LPC1769) is written:

24.4.1   Rules for Single Edge Controlled PWM Outputs
  [*]All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0.
  [*]Each PWM output will go low when its match value is reached. If no match occurs (i.e. the match value is greater than the PWM rate), the PWM output remains continuously high.

I set MR2 to 0 (it's the second channel of PWM1 on pin 3.25 of LPC1769), but the pin stays stable high. Why?

I know I can configure the pin as GPIO when the duty cycle is 0%, but it's better to use PWM peripherals.