lpcware

LPC1768: Sporadic wrong ADC values read from register when debugger is running.

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by Ronny Friedrich on Tue Apr 12 09:02:25 MST 2016
Hello,

I noticed recently some strange "spikes" in measured ADC values using the ADC running in burst mode using the DMA on MCB1700 evalboard.
The wrong samples are in most cases above 4000, however there are also some other samples with extrem deviations.

After no spikes can be seen directly at the ADC pin (ADC0.2) via scope I simplified the code to polling the "Done" Flag and read the register directly:


#include "inttypes.h"
#include "stdbool.h"
#include "LPC17xx.h"
#include "ADC_LPC175x_6x.h"
#include "SCU_LPC175x_6x.h"
#include "CLOCK_LPC175x_6x.h"

int main ( void )
{
    static uint32_t measCnt = 0, errCnt = 0, temp, last_temp;
    PINSEL_CFG_Type pinCfg;
   
    LPC_SC->PCONP      |= CLKPWR_PCONP_PCAD;
   
    pinCfg.Funcnum = 1;
    pinCfg.Pinnum  = 25;
    pinCfg.Portnum = 0;
    PINSEL_ConfigPin(&pinCfg);

    LPC_GPIO2->FIODIR |= (1<<5);
    LPC_GPIO2->FIODIR |= (1<<6);
   
    LPC_ADC->ADCR              = ADC_CR_PDN;
    LPC_ADC->ADINTEN           = 0;
    LPC_ADC->ADCR              |= (1UL<<2);  /* Bits 7:0 Channel select */
    LPC_ADC->ADCR              |= (6<<8);    /* Bits 15:8 ClkDiv        */
    LPC_ADC->ADCR              |= ADC_CR_BURST; /* Start Burst          */
   
    __disable_irq();
    while ( 1 )
    {
       LPC_GPIO2->FIOSET = (1UL<<6UL);   
       while ( (LPC_ADC->ADGDR & ADC_DR_DONE_FLAG) == 0) {};
       LPC_GPIO2->FIOCLR = (1UL<<6UL);   

       temp = ADC_DR_RESULT(LPC_ADC->ADGDR);
       if ( (temp > last_temp+160) || (temp < last_temp-160) )
       {
            errCnt++;
            LPC_GPIO2->FIOSET = (1UL<<5UL);   
       }
       else
       {
           measCnt++;
           LPC_GPIO2->FIOCLR = (1UL<<5UL);   
       }
       last_temp = temp;
    }
}   


The code above should run with a samplingrate of ~55kHz which can be seen at P2.6. "PCLK_ADC0"
should run at 25MHz resulting at a ADC frequency of approx. 8 MHz which is below the maximum allowed
ADC clock of 13 MHz.

When no debugger is attached, there is no pulse at P2.5 at all. However, with debugger attached to the
target "errCnt" does increment quite often and a few pulses at P2.5 can be measured per second.

When ClkDiv is increased to values above 0x80 almost no pulses can be seen anymore.

Is there a known issue about the maximum allowed samplingrate / adc clock when a JTAG session is
active? I know about the ADC hw designguidelines mentioning noise influences when debugging the
target, but this seems to be a different issue.

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