LPC1778 CAN Block Registers

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LPC1778 CAN Block Registers

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Sat Oct 25 16:49:34 MST 2014
The same CAN block may be used in other MCUs but my board is using the LPC1778.
I am referring to UM10470 Rev 3 12th March 2014.

The 'bus error' bits (16..23) in the 'Interrupt and Capture' register (for each implemented CAN block)
appear to be 'stickey'.

Once a bus error has occured, subsequent valid transmissions(s) or reception(s) do not appear to
'reset' these bits. They only change (but never zero) if another bus error is observed. [Or a chip reset is given.]

From the UM 20.7.4 p572

Quote:
The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read
from CANxICR, regardless of whether part or all of the register is read. This means that
software should always read CANxICR as a word, and process and deal with all bits of the
register as appropriate for the application.



How may I reset (clear) these bits in this read-only register programatically (i.e. via code)?
I have tried reading the register (bits 1..10 are documented as clearing on read) before, during, and after
placing the block in and then out of 'reset mode' [via the CAN Mode register] but to no avail.

On a, possibly, similar note, the 'transmission complete' bit [bit 3] in the CAN Global Status register
remains clear (unset) [after a failed transmission] even after an 'Abort' command is given [via the
CAN Command register]. It only becomes set again after a successful transmission [or chip reset].

Again, how can I cause this bit to be set (i.e. error to be cleared) via code.

Regards, Mike.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by MikeSimmonds on Sat Oct 25 18:08:07 MST 2014
I see that UM10470 rev 3.1 was released on 15th September 2014, but I see no apparent changes
to the documentation of the CAN 'Global Status' and 'Interrupt and Capture' registers.

Mike.
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