Content originally posted in LPCWare by Herrbert on Tue Nov 24 05:12:44 MST 2015
Hi Forum,
I have a problem with the timing specification of the EMC of LPC1788.
The SD-RAM we use (Micron MT48LC4M32B2P-6A IT) specifies a data hold time of min. 3 ns.
This seems to not be compatible with the LPC1788 EMCs specification of a data input hold time (th) of min. (FBCLKDLY+1) * 0.25 +3.7 ns (so minimal 3.95 ns).
The primecell documentation of the EMC (IMHO this is PL172) explicitly says that the RAM is compatible.
Is there an error in the datasheet? Do I miss something?
Thanks!
