LPC1788 Cannot find debug component in ROM Table

[lpcware]

Content originally posted in LPCWare by RKRobinson on Tue Jan 22 08:39:11 MST 2013


Hi,

I have or should I say had a uEZGUI178843WQR development board from FDI. I was in the process of modifying the standard LIBMEM loader to allow programming of the external NOR flash. I had added the code to configure the EMC to enable access to the external NOR flash at 0x80000000. It worked to the extent that the LIBMEM CFI driver recognized the external FLASH and returned a successful result code. When I tried to use the loader for the first time without attempting program external FLASH only the internal device FLASH. I was unable to communicate with the processor, I returned to using the original loader and have attempted to erase the internal FLASH with Seggers ARM Flasher tool  without success. So my question is can anyone see a reason that the code below would cause processor damage? Any help wold be greatly appreciated.

Regards,

Richard.





/*****************************************************************************
* RPC Loader for LPC177x_8x                                                 *
*                                                                           *
* Copyright (c) 2010 Rowley Associates Limited.                             *
*                                                                           *
* This file may be distributed under the terms of the License Agreement     *
* provided with this software.                                              *
*                                                                           *
* THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE   *
* WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
*****************************************************************************/

#include <liblpc1000.h>
#include <LPC1788.h>
#include <libmem.h>
#include <libmem_loader.h>
#include <string.h>
#include <limits.h>

extern uint8_t __SRAM_segment_start__;
extern uint8_t __SRAM_segment_used_end__;

int
main(uint32_t flags, uint32_t param)
{
  size_t ram_size;
  uint32_t fosc = flags & LIBMEM_RPC_LOADER_FLAG_PARAM ? param : 0;
  const char *error_string = 0;
  int res;
  uint32_t cclk_frequency;


  uint8_t *flash2_start = (uint8_t *)0x80000000;
  libmem_flash_info_t flash2_info;
  const int flash2_max_geometry_regions = 4;
  libmem_geometry_t flash2_geometry[flash2_max_geometry_regions];
  libmem_driver_handle_t flash1_handle,flash2_handle;


  cclk_frequency = liblpc1000_lpc177x_8x_get_cclk(fosc);
  ram_size = liblpc1000_get_local_sram_size();

  //
  //Initialize P4 30 Chip select 0
  //
  IOCON_P4_30_REG |= 1;
  //
  //Initialize P4 24 Output Enable
  //
  IOCON_P4_24_REG |=1;
  //
  //Initialize P4 25 Write Enable
  //
  IOCON_P4_25_REG |=1;

  //
  //Initialize Address Bus P4-0 to P4-23
  //
  IOCON_P4_00_REG   |= 1;
  IOCON_P4_01_REG   |= 1;
  IOCON_P4_02_REG   |= 1;
  IOCON_P4_03_REG   |= 1;
  IOCON_P4_04_REG   |= 1;
  IOCON_P4_05_REG   |= 1;
  IOCON_P4_06_REG   |= 1;
  IOCON_P4_07_REG   |= 1;
  IOCON_P4_08_REG   |= 1;
  IOCON_P4_09_REG   |= 1;
  IOCON_P4_10_REG   |= 1;
  IOCON_P4_11_REG   |= 1;
  IOCON_P4_12_REG   |= 1;
  IOCON_P4_13_REG   |= 1;
  IOCON_P4_14_REG   |= 1;
  IOCON_P4_15_REG   |= 1;
  IOCON_P4_16_REG   |= 1;
  IOCON_P4_17_REG   |= 1;
  IOCON_P4_18_REG   |= 1;
  IOCON_P4_19_REG   |= 1;
  IOCON_P4_20_REG   |= 1;
  IOCON_P4_21_REG   |= 1;
  IOCON_P4_22_REG   |= 1;
  IOCON_P4_23_REG   |= 1;

  //
  //Initialize Data Bus P3-0 to P3-31
  //
  IOCON_P3_00_REG     |= 1;
  IOCON_P3_01_REG     |= 1;
  IOCON_P3_02_REG     |= 1;
  IOCON_P3_03_REG     |= 1;
  IOCON_P3_04_REG     |= 1;
  IOCON_P3_05_REG     |= 1;
  IOCON_P3_06_REG     |= 1;
  IOCON_P3_07_REG     |= 1;
  IOCON_P3_08_REG     |= 1;
  IOCON_P3_09_REG     |= 1;
  IOCON_P3_10_REG     |= 1;
  IOCON_P3_11_REG     |= 1;
  IOCON_P3_12_REG     |= 1;
  IOCON_P3_13_REG     |= 1;
  IOCON_P3_14_REG     |= 1;
  IOCON_P3_15_REG     |= 1;
  IOCON_P3_16_REG     |= 1;
  IOCON_P3_17_REG     |= 1;
  IOCON_P3_18_REG     |= 1;
  IOCON_P3_19_REG     |= 1;
  IOCON_P3_20_REG     |= 1;
  IOCON_P3_21_REG     |= 1;
  IOCON_P3_22_REG     |= 1;
  IOCON_P3_23_REG     |= 1;
  IOCON_P3_24_REG     |= 1;
  IOCON_P3_25_REG     |= 1;
  IOCON_P3_26_REG     |= 1;
  IOCON_P3_27_REG     |= 1;
  IOCON_P3_28_REG     |= 1;
  IOCON_P3_29_REG     |= 1;
  IOCON_P3_30_REG     |= 1;
  IOCON_P3_31_REG     |= 1;

  //
  //Initialize EMC Clock DIV 2 for 120MHz CLK
  //
  EMCCLKSEL_REG = 1;
  //
  //EMC control register
  //
  EMCControl_REG  = 0x00000001;

  //
  //EMC config Register
  //
  EMCConfig_REG   = 0x00000000;

  //
  //Initialize Static Configuration Register 0
  //
  EMCStaticConfig0_REG =  1 |  //Bus width 16 bits
                          (1<<7);
                         

  //
  //Initialize Static Output Enable Wait Register 0
  //
  EMCStaticWaitOen0_REG = 0x03;
  //
  //Initialize Static Read Wait Register 0
  //
  EMCStaticWaitRd0_REG  = 0x05;
  //
  //Initialize Static Page Wait Register 0
  //
  EMCStaticWaitPage0_REG = 0x8;
  //
  //Initialize Static Write Enable Wait Register 0
  //
  EMCStaticWaitWen0_REG = 0x03;
  //
  //Initialize Static Write Wait Register 0
  //
  EMCStaticWaitWr0_REG = 0x0A;
  //
  //Initialize Static Turn Wait Register 0
  //
  EMCStaticWaitTurn0_REG = 0x07;
  //
  //Initialize System Controls & Status Register
  //
  SCS_REG =1; //All addresses are byte addresses


  if (ram_size > 0)
    {
      uint32_t isp_ram_backup[8];


      if (flags & LIBMEM_RPC_LOADER_FLAG_PRESERVE_STATE)
        {
          /* Backup RAM used by ISP functions */
          memcpy(isp_ram_backup, &__SRAM_segment_start__ + ram_size - 32, 32);
        }

        res = libmem_register_cfi_driver(&flash2_handle,
                                              flash2_start,
                                              flash2_geometry,
                                              flash2_max_geometry_regions,
                                              &flash2_info);



      /* Initialise External FLASH drivers */
      res = liblpc1000_register_libmem_driver(&flash1_handle, cclk_frequency);

      if (res == LIBMEM_STATUS_SUCCESS)
        {
          /* Run the loader - use the unused RAM minus the 32 bytes used by ISP as the RPC communication buffer */
          libmem_rpc_loader_start(&__SRAM_segment_used_end__, &__SRAM_segment_start__ + ram_size - 33);
        }

      if (flags & LIBMEM_RPC_LOADER_FLAG_PRESERVE_STATE)
        {
          /* Restore RAM used by ISP functions */
          memcpy(&__SRAM_segment_start__ + ram_size - 32, isp_ram_backup, 32);
        }
    }     
  else
    {
      res = LIBMEM_STATUS_ERROR;
      error_string = "unknown target device";
    }

  libmem_rpc_loader_exit(res, error_string);

  return 0;
}

[lpcware]

Content originally posted in LPCWare by RKRobinson on Thu Jan 24 09:23:44 MST 2013
Hi,
Thanks for the reply. This did resolve the issue.
Richard.

[lpcware]

Content originally posted in LPCWare by Wouter on Wed Jan 23 06:15:57 MST 2013
Most probably you did not damage your LPC, but only locked from SWD/JTAG communication (e.g. due to invalid settings).

Try booting into ISP mode by pulling the ISP pin low, press reset button, release reset button and then release the ISP pin. According to the schematic of the board, the ISP pin is connected to the 6-pin header J3.