Design guidlines for LPC1768 at 100MHz

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by johndpar on Thu Apr 03 05:20:23 MST 2014
This is not the usual question about how to set the PLL and dividers. That bit is quite easy!

We have some issues running the LPC1768 at 100MHz, in particular the CAN peripheral does not always accept writes to its registers.

(12MHz crystal with 400MHz PLL and divide by 4 to get 100MHz)

Having dropped the speed to 80MHz the system is working well.

We suspect that our board layout is a problem.

Do you have any design guidelines for placement of decoupling capacitors, their type and value?


John Parker