lpcware

Question on LPC1788 Interrupt latency

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by EReyes on Tue Mar 27 19:00:41 MST 2012
I have an application that requires responding to an input capture interrupt within 6 microseconds. At the same time, the LCD controller is active, and some parts of the application code could be running out of external SDRAM, although critical code will be placed on internal memory for obvious reasons.

In the user manual, section 2.5.1, a similar scenario is described (executing code out of external memory while the LCD DMA is active). I'm having trouble understanding how the system would react to a hypothetical situation like this:

- The LCD DMA has the highest priority
- Code from external SDRAM is executing, and accessing the SDRAM itself (a screen contents update comes to mind)
- The CPU is stalled waiting for the LCD DMA to finish
- An capture interrupt occurs

Lets assume the ISR for this capture input resides in internal memory. Is the CPU left on a stalled state until the LCD DMA finishes or is it switched immediately to execution out of internal memory? If it is the former, what kind of increase in interrupt response time should I expect considering standard operating conditions? (CPU at 120 MHz, SDRAM clock at 60 MHz).

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