lpcware

I2C Clock Rate

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Dave on Mon Jan 07 13:12:07 MST 2013
I'm having difficulties understanding what's going on with the I2C clock and am hoping somebody can shed some light on this for me.

I'm using the LPC1788 processor, and am using the system_LPC177x8x.C file for setting up the clocks.

My target has an external 12Mhz crystal, and the clocks are setup as follows:
<code>
PLL0 Configuration: 
   MSEL=10, PSEL=1

PLL1 Configuration: 
   MSEL=8, PSEL=2

CPU Clock: 
   CCLKDIV=1
   CCLKSEL = PLLO

USB Clock:
   Divider is 4
   Clock output from PLL1

EMC Clock:
   EMCDIV=1

Peripheral Clock:
   PCLKDIV=2

Clock Output Configuraton Register (CLKOUTCFG)
   CLKOUTSEL=CPU clock
   CLKOUTDIV=1
   CLKOUT enable= unchecked

Flash Accelerator=checked
   FLASHTIM=6 CPU clocks
</code>

According to the user's manual, the equation for setting the clock speed is as follows:

<code>
                          PCLKI2C
I2Cbitfrequency=   ---------------------
                      I2CSCLH + I2CSCLL
</code>

and in Table 502 (Example I2C clock rates), when PCLK is 60Mhz, you should get a 400kHz clock rate if I2SCLL + I2SCLH equals 150

so here is my problem:

When I set I2SCLL to 75, and I2SCLH to 75, I get the following waveform on SCL (P5.3):

http://www.lpcware.com/content/image/336khz-clockjpg-0

Am I missing something here?

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