lpcware

LPC1768 - Race condition within CAN peripheral?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by johndpar on Wed Nov 20 02:15:54 MST 2013
Hi all

This processor is being used in a large number of CAN slaves.

The setup is this:

[list]
  [*]LPC1768 on custom pcb with 12MHz crystal, configured to run at 417.6MHz.
  [*]CAN peripheral configured to run at 500kbps bit rate
  [*]CMSIS driver library (latest version)
  [*]CodeSourcery IDE - latest version
[/list]

With the debug code the system never fails
With the release code the system sometimes fails with the slave having the wrong bit rate and therefore entering "ERROR PASSIVE"

Further examination shows the bit rate register is set to the "reset" condition as if the code in can_setBaudRate had not run.

Looking at the disassembled compiled code, in the debug version there are several instructions between setting the CANxMOD register to RM, and writing the BTR register value.

In the release version, the RM mode setting and BTR write are consecutive instructions.

We changed the code so that even in the release version there are several instructions between setting the RM mode and writing the BTR and now the system seems to wor with both debug and release versions.

So it would seem that it may take "some time" for the RM bit to take effect!

Can anyone at NXP confirm if this is the case?
Has anyone else seen this problem?


Actually I think this http://www.lpcware.com/content/forum/warning-gcc-optim-issue-with-some-cmsis-drivers is the same issue but would like someone from NXP to investigate.

Regards

John

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