Content originally posted in LPCWare by schisanoa on Tue Jun 24 07:57:05 MST 2014
Thanks MC, I've already found the documents that you suggest, but I have a question.
My configuration is with only 1 SDRAM connected on the bus, I matched the impedance suggested in the doc and also the layer stackup.
The question is: looking the first document, at page 19, section 2.7, is suggested to keep "bus signals as short as possible and capacitive loading to a minimum", and after this, there is the Rule 1, that talk about net length, but if I have correctly understant is referred to multiple SDRAM configuration, that is not my configuration and the document never talk about single SDRAM data, address or command line wire length.
From this I suppose that with single SDRAM is not required to match the data bus wire length by using of meanders, is it correct?
And if it is, why if I look at the LPC1788 OEM Board from EA seems that they used meanders to match the data ram signal?
Sorry if my question is a little confused, ask me if it is not clear
