LPC1778, IS42S16400F SRAM problems...

[lpcware]

Content originally posted in LPCWare by cgroen on Wed Sep 12 10:20:56 MST 2012
Hello,
I seem to have run into some of the same problems as some other users of the LPC1778...
I have been reading all the threads regarding the SDRAM setup, but so far without success.
I have a custom designed board (everything in BGA, so a little hard to probe ;)), CPU is LPC1778, SDRAM is a ISSI IS42S16400F (64 Mbit in 16 bit mode). I have been testing various setups from the NXP samples, but is stuck!

I run the CPU at 120 MHz and the EMC at 60 MHz (have also tried running much slower, no change). I do the setup of the EMC, and perform a small test of the SDRAM (copy 8KByte from the flash to the SDRAM). When I compare the SDRAM with the FLASH data, I almost everytime gets a verify error at address offset 0x1F0 (once in a while it shows at 0x1F6 instead). When I manually (Keil) modify the SDRAM area, the contnts will sometimes flicker and get destroyed, if the code is allowed to run fullspeed, I see the verify error as detailed above....
I have also used the "calibration" examples, it would not find a suitable timing, and bail out everytime with the safe value (which also did not work)

Maybe one of you "EMC Pro" has some input as to what can be wrong ??

The code as it looks right now (also tried in "normal" mode for the pins, same result):


static void pinConfig(void) {

  LPC_IOCON->P3_0 |= 0x201; /* D0 @ P3.0 */
  LPC_IOCON->P3_1 |= 0x201; /* D1 @ P3.1 */
  LPC_IOCON->P3_2 |= 0x201; /* D2 @ P3.2 */
  LPC_IOCON->P3_3 |= 0x201; /* D3 @ P3.3 */

  LPC_IOCON->P3_4 |= 0x201; /* D4 @ P3.4 */
  LPC_IOCON->P3_5 |= 0x201; /* D5 @ P3.5 */
  LPC_IOCON->P3_6 |= 0x201; /* D6 @ P3.6 */
  LPC_IOCON->P3_7 |= 0x201; /* D7 @ P3.7 */

  LPC_IOCON->P3_8 |= 0x201; /* D8 @ P3.8 */
  LPC_IOCON->P3_9 |= 0x201; /* D9 @ P3.9 */
  LPC_IOCON->P3_10 |= 0x201; /* D10 @ P3.10 */
  LPC_IOCON->P3_11 |= 0x201; /* D11 @ P3.11 */

  LPC_IOCON->P3_12 |= 0x201; /* D12 @ P3.12 */
  LPC_IOCON->P3_13 |= 0x201; /* D13 @ P3.13 */
  LPC_IOCON->P3_14 |= 0x201; /* D14 @ P3.14 */
  LPC_IOCON->P3_15 |= 0x201; /* D15 @ P3.15 */


  LPC_IOCON->P4_0 |= 0x201; /* A0 @ P4.0 */
  LPC_IOCON->P4_1 |= 0x201; /* A1 @ P4.1 */
  LPC_IOCON->P4_2 |= 0x201; /* A2 @ P4.2 */
  LPC_IOCON->P4_3 |= 0x201; /* A3 @ P4.3 */

  LPC_IOCON->P4_4 |= 0x201; /* A4 @ P4.4 */
  LPC_IOCON->P4_5 |= 0x201; /* A5 @ P4.5 */
  LPC_IOCON->P4_6 |= 0x201; /* A6 @ P4.6 */
  LPC_IOCON->P4_7 |= 0x201; /* A7 @ P4.7 */

  LPC_IOCON->P4_8 |= 0x201; /* A8 @ P4.8 */
  LPC_IOCON->P4_9 |= 0x201; /* A9 @ P4.9 */
  LPC_IOCON->P4_10 |= 0x201; /* A10 @ P4.10 */
  LPC_IOCON->P4_11 |= 0x201; /* A11 @ P4.11 */

  LPC_IOCON->P4_13 |= 0x201; /* A13 @ P4.13 */
  LPC_IOCON->P4_14 |= 0x201; /* A14 @ P4.14 */


  LPC_IOCON->P4_25 |= 0x201; /* WEN @ P4.25 */


  LPC_IOCON->P2_16 |= 0x201; /* CASN @ P2.16 */
  LPC_IOCON->P2_17 |= 0x201; /* RASN @ P2.17 */
  LPC_IOCON->P2_18 |= 0x201; /* CLK[0] @ P2.18 */

  LPC_IOCON->P2_20 |= 0x201; /* DYCSN[0] @ P2.20 */

  LPC_IOCON->P2_24 |= 0x201; /* CKE[0] @ P2.24 */

  LPC_IOCON->P2_28 |= 0x201; /* DQM[0] @ P2.28 */
  LPC_IOCON->P2_29 |= 0x201; /* DQM[1] @ P2.29 */
}

/******************************************************************************
*
* Description:
*    Initialize the SDRAM
*
*****************************************************************************/
uint32_t sdram_init (void)
{
  uint32_t i, dwtemp = dwtemp;
  uint16_t wtemp = wtemp;

  LPC_SC->PCONP     |= 0x00000800;
  LPC_SC->EMCDLYCTL   = 0x00001010;
  LPC_EMC->Control   = 0x00000001;
  LPC_EMC->Config    = 0x00000000;

  pinConfig();

  /* Configure memory layout, but MUST DISABLE BUFFERs during configuration */
  /* 64MB, 4Mx16, 4 banks, row=12, column=8 */
  LPC_EMC->DynamicConfig0    = 0x00000280;

  //Timing for 60 MHz Bus
  LPC_EMC->DynamicRasCas0    = 0x00000202; /* 2 RAS, 2 CAS latency */
  LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
  LPC_EMC->DynamicRP         = 0x00000002; /* ( n + 1 ) -> 2 clock cycles */
  LPC_EMC->DynamicRAS        = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
  LPC_EMC->DynamicSREX       = 0x00000007; /* ( n + 1 ) -> 6 clock cycles */
  LPC_EMC->DynamicAPR        = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
  LPC_EMC->DynamicDAL        = 0x00000005; /* ( n ) -> 3 clock cycles */
  LPC_EMC->DynamicWR         = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
  LPC_EMC->DynamicRC         = 0x00000005; /* ( n + 1 ) -> 5 clock cycles */
  LPC_EMC->DynamicRFC        = 0x00000005; /* ( n + 1 ) -> 5 clock cycles */
  LPC_EMC->DynamicXSR        = 0x00000007; /* ( n + 1 ) -> 6 clock cycles */
  LPC_EMC->DynamicRRD        = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
  LPC_EMC->DynamicMRD        = 0x00000002; /* ( n + 1 ) -> 2 clock cycles */

  os_dly_wait(10);                         /* wait 100ms */
  LPC_EMC->DynamicControl    = 0x00000183; /* Issue NOP command */
  os_dly_wait(20);                         /* wait 200ms */
  LPC_EMC->DynamicControl    = 0x00000103; /* Issue PALL command */
  LPC_EMC->DynamicRefresh    = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
  for(i = 0; i < 0x80; i++);               /* wait 128 AHB clock cycles */

  //Timing for 60MHz Bus
  LPC_EMC->DynamicRefresh    = 0x0000003A; /* ( n * 16 ) -> 928 clock cycles -> 15.466uS at 60MHz <= 15.625uS ( 64ms / 4096 row ) */

  LPC_EMC->DynamicControl    = 0x00000083; /* Issue MODE command */

  //Timing for 48/60/72MHZ Bus
  dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x33<<9))); /* 8 burst, 3 CAS latency */

LPC_EMC->DynamicControl    = 0x00000000; /* Issue NORMAL command */

//[re]enable buffers
  LPC_EMC->DynamicConfig0    |= 0x00080000;

  os_dly_wait(20);                         /* wait 200ms */

  return TRUE;
}

[lpcware]

Content originally posted in LPCWare by cgroen on Wed Sep 12 14:09:27 MST 2012
Oh my...
Thanks a LOT Karl, I have been studying the mode register stuff, the address bits etc, and I was 99.9% sure I had it right, you just proved that it was the 0.1% that was right :D

Thanks for the help, you just saved my day!
Now I "only" have to port around 150.000 lines of code to the new platform :)

[lpcware]

Content originally posted in LPCWare by Karl on Wed Sep 12 12:08:40 MST 2012
Hi,

I could probably make a good living from SDRAM consultations :-)

Try changing this line:
<code>
dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x23<<11))); /* 8 burst, 2 CAS latency */
</code>

That sets the mode register to two CAS cycles, in line with the setting in ...RASCAS0 above.
And the famous shift value has to be 11: 8 columns + 2 bank bits + 1 (16-bit bus)

Best regards,
Karl