AHB Arbitration Register

[lpcware]

Content originally posted in LPCWare by rmoss on Wed Sep 12 06:18:25 MST 2012
We have currently in Production the LCP2478 with 7" screen working fine.  There was an issue with screen tear on the screen initially, however after setting up the AHBCFG1 Register on the LPC2478 things work fine.

AHBCFG1       =     (0x0 << 31)     // 31 - reserved
                    | (0x5 << 28)     // 30:28 - Priority for LCD
                    | (0x0 << 27)     // 27 - reserved
                    | (0x1 << 24)     // 26:24 - Priority for USB
                    | (0x0 << 23)     // 23 reserved
                    | (0x2 << 20)     // 22:20 - Priority for AHB1
                    | (0x0 << 19)     // 19: reserved
                    | (0x3 << 16)     // 18:16 EP2 - Priority for GPDMA
                    | (0x0 << 15)     // 15 reserved
                    | (0x4 << 12)     // 14:12 EP1 - Priority for CPU
                    | (0x0 << 11)     // 11 reserved
                    | (0x1 << 8)      // 10:8 default master
                    | (0x4 << 4)      // 7:4 quantum size
                    | (0x0 << 3)      // 3 quantum type
                    | (0x2 << 1)      // 2:1 break burst
                    | 0x0;            // 0  scheduler

Now I am porting the project to the LPC1788 and once again have the screen tear issue using the default AHB Arbitrator Register settings.  Per the LPC1788 User Manual, I have set the Matrix Arbitration register to 0x00000C09.  This improved things greatly, however there is still an occasional screen tear even when sitting idle with one bmp displayed.  I am not using DMA for the screen buffer.

Thanks

[lpcware]

Content originally posted in LPCWare by rmoss on Wed Sep 19 10:41:54 MST 2012
Update.  Even though I set the AHB Arbitrator Register to allow the LCD to have top priority, as the manual suggests there is still a limit due to the SDRAM max speed of 80 MHz.  This was also in the manual.  I was running at 120MHz with a divide by 2 for the SDRAM bus meaning the SDRAM is now only 60MHz.  By lowering the CPU to 80MHz and no divided by in the SDRAM registers, the screen tear has gone away and performance seems better.  The LPC2478 had the bus contention issue when using a display of this size, but now the 1788 has a bottleneck with respect to the SDRAM speed.  Why would NXP limit the SDRAM bus to such a slow speed compared to what the LPC1788 can do (120MHz)?