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LPC1768 + GPDMA + SSP + Burst size + memory boundary/alignment

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by solsal on Thu Aug 23 16:18:14 MST 2012
LPC1768 + GPDMA + SSP + Burst size + memory boundary
Hi,

please refer to UM10360 page:611

my question is around these items:

LPC1768 + GPDMA + Burst size + memory boundary/alignment

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31.6.4 Address generation
Address generation can be either incrementing or non-incrementing (address wrapping is
not supported).
Some devices, especially memories, disallow burst accesses across certain address
boundaries. The DMA controller assumes that this is the case with any source or
destination area, which is configured for incrementing addressing. This boundary is
assumed to be aligned with the specified burst size. For example, if the channel is set for
16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is
address bits [5:0] equal 0). If a DMA burst is to cross one of these boundaries, then,
instead of a burst, that transfer is split into separate AHB transactions.

31.6.4.1 Word-aligned transfers across a boundary
The channel is configured for 16-transfer bursts, each transfer 32-bits wide, to a
destination for which address incrementing is enabled. The start address for the current
burst is 0x0C000024, the next boundary (calculated from the burst size and transfer
width) is 0x0C000040.
The transfer will be split into two AHB transactions:
• a 7-transfer burst starting at address 0x0C000024
• a 9-transfer burst starting at address 0x0C000040.

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1. what do those paragraphs mean?

2. Q: How should this operation be done?

I want to send an array of 1024 bytes to SSP0( spi ) and receive 1024 bytes from it to another array of 1024 bytes.
(send and receive are Simultaneous : this is a full duplex operation then which of M2P/P2M/M2M ???)

( this is repeatedly done every 100ms )

"SSP0(SPI) hardware is connected to another 8bit_uC_SPI"

by using SSP0+GPDMA+BURST+ "two 1024 bytes array in sram"

what is the exact solution for this question?

( I studied the USER MANUAL UM10360 but it is not clear enough and
I didn't find clean information around this )

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I have already done this operation on ( AT91SAM7X256(master) + atmega32(slave) ) on keil(arm) + codevision(AVR)....

now I want to do this by ( LPC1768(master) + atmega32(slave) ) , but this
GPDMA+BURST+memory alignment .... is confusing thing.

the slave device is working properly on previous design and I need to run Master(lpc1768) properly.

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please share your knowledge ,

regards.

www.nxp.com/documents/user_manual/UM10360.pdf

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