UART used on for full duplex RS422 : RX bytes lost when flushing TX FIFO

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by renonbenoit on Mon Mar 16 09:07:24 MST 2015

We are using the UART0 peripheral of the LPC1768 for a full duplex communication on a RS422 physical link between a ECU (embedding LPC1768) and a PC (classical COM port terminal).

Both ECU and PC transmit 300-bytes-long frames periodically at 100ms (multi-master / full-duplex communication).
The problem is that we are loosing bytes on the ECU side, i.e. the LPC1768 RX FIFO is loosing bytes.
This problems occurs almost every hour.

We developped a software driver for UART which uses interrupts both for RX and TX events :
- RX FIFO trigger level is set to 0
- RDA interrupts are handled as well as CTI interrupts to build-up our RX SW buffer
- RLS interrupts are handled to notify errors
- THRE interrupts are handled to fill the TX FIFO as fast as possible
- the driver systematically flushes out the TX FIFO of the UART (using bit 2 of FCR register) before sending a new frame

We instrumented our code and spent hours debugging our driver to finally conclude that the LPC1768 may not handle correctly simultaneous TX and RX FIFO activities.

Here is a summary of our obsevations :
1) Removing the code that flushes TX FIFO before each transmission seems to solve the problem
2) Number of lost bytes is very often (75%) 13 bytes. We guess there is something around CTI handling because this kind of event is supposed to occur when a byte is in the RX FIFO since more than 3.5 character-times, and the RX FIFO is 16 bytes long.

Have you already some customer feedback about such things ? Is there a known bug in UART module that does not appear in errata sheets ?

Thank you in advance for your help