lpcware

Interfacing with SDRAM

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by MindBender on Wed Jul 15 06:09:29 MST 2015
Are the SDRAM bank select lines BA0 and BA1 always connected to LPC17xx address lines A13 and A14, regardless the SDRAM size? Of do we have to shift them down accordingly with smaller memories?
The manual (UM10470) says in chapter 9.13.19 on page 196:
[color=#00f]For example, for a chip select connected to:[/color]
[list]
[color=#00f]  [*]a 32 bit wide memory device, choose a 32 bit wide address mapping.[/color]
[color=#00f]  [*]a 16 bit wide memory device, choose a 16 bit wide address mapping.[/color]
[color=#00f]  [*]four x 8 bit wide memory devices, choose a 32 bit wide address mapping.[/color]
[color=#00f]  [*]two x 8 bit wide memory devices, choose a 16 bit wide address mapping.[/color]
[/list]
[color=#00f]The SDRAM bank select pins BA1 and BA0 are connected to address lines A14 and A13,
respectively.[/color]

It is unclear to me if the remark on BA0 and BA1 on the last line still belongs to the example above, or that they always need to be connected like that.

Outcomes