LPC1769 pending interrupts

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LPC1769 pending interrupts

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by wlamers on Wed Aug 29 11:12:56 MST 2012
Hello All,

I am facing a weird problem with the external interrupts of the LPC17xx series.

I have an external button set to external interrupt 1, falling edge with both an internal as an external pull-up resistor (p2.11):

PinCfg.Funcnum = 1;
PinCfg.OpenDrain = 0;
PinCfg.Pinmode = PINSEL_PINMODE_PULLUP;
PinCfg.Pinnum = 11;
PinCfg.Portnum = 2;
PINSEL_ConfigPin(&PinCfg);
GPIO_SetDir(2,((uint32_t)1<<11),0);

And:
EXTICfg.EXTI_Line = EXTI_EINT1;
EXTICfg.EXTI_Mode = EXTI_MODE_EDGE_SENSITIVE;
EXTICfg.EXTI_polarity = EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE;
EXTI_Config(&EXTICfg);
EXTI_ClearEXTIFlag(EXTI_EINT1);

And:

NVIC_SetPriority(EINT1_IRQn,1);
NVIC_EnableIRQ(EINT1_IRQn);


This is a part of the ISR (including 200ms button debouncing timer):

void EINT1_IRQHandler(void)
{
EXTI_ClearEXTIFlag(1);

uint32_t tim1Cnt = LPC_TIM1->TC;

if (tim1Cnt > ButtDebounceUs)
{
LPC_TIM1->TC = 0x00000000;

// Do work here
}
}

The "Do work here" section could take some time (e.g. more than 200ms in some cases). This is intended and no problem for the further execution of the program.

The problem is that when the ISR is entered first and I press the button a second time while the ISR is executing (this has to be done fast) a pending interrupt is set and causes the ISR to execute again if it has ended for the first time. This is normal behaviour I guess, since EXTI_ClearEXTIFlag(1) does not clear any pending interrupts in the NVIC. So I added NVIC_ClearPendingIRQ(EINT1_IRQn) to clear the new pending interrupts on several locations in the ISR code to be sure the pending interrupt(s) is/are cleared. Strangely enough this does not work at all.

Some my question is, how can I read the pending interrupts via JTAG/debugger (memory address?). And what is going on here? Can someone explain this behaviour and maybe has a clue how to fix it?

Thanks!





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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by wlamers on Thu Aug 30 00:38:18 MST 2012
Hello Lien,

Yes I have read the text which explains going to pending. That is why I tried to clear the pending state. Unfortunately this does not work. But your tip to move the line EXTI_ClearEXTIFlag(1) to the end of ISR does work! All other external interrupt requests are simply ignored (this in contrast to disabling the NVIC for the particular ISR and then enabling it on the end. You get still a pending ISR request then).

This is offcourse great, but I am still wondering why clearing the pending state does not work. Maybe this is only the case for GPIO interrupts?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Lien.Nguyen on Wed Aug 29 20:44:00 MST 2012
Hi,
In UM, section 34.4.2.9.1, it says that when there is a new interrupt comming while the processor is in ISR, the state of the interrupt changes to pending and active. In this case, if software writes to the corresponding interrupt clear-pending register bit, the state of the interrupt changes to active.

In you case, to fix this problem, I think that you can move the line EXTI_ClearEXTIFlag(1) to the end of ISR. The pulse on the interrupt pin only be recognized until the coressponding bit in EXTINT is cleared.
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