Content originally posted in LPCWare by Lien.Nguyen on Wed Aug 29 20:44:00 MST 2012
Hi,
In UM, section 34.4.2.9.1, it says that when there is a new interrupt comming while the processor is in ISR, the state of the interrupt changes to pending and active. In this case, if software writes to the corresponding interrupt clear-pending register bit, the state of the interrupt changes to active.
In you case, to fix this problem, I think that you can move the line EXTI_ClearEXTIFlag(1) to the end of ISR. The pulse on the interrupt pin only be recognized until the coressponding bit in EXTINT is cleared.