lpcware

Decision on choosing crystal alongside PLL

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by mohammadyou on Sun Oct 25 05:29:27 MST 2015
I have been told for noisy environments having smaller value of external crystal is better and base on the user manual that says "A smaller value of the PLL N as well as smaller value of M Both result in better PLL operational stability and lower jitter "
now consider these situations :
1- 1   Mhz crystal Fcco=300Mhz  Cpu(core)=100Mhz -> M=150 N=1 CPU div =3
2- 10 Mhz crystal Fcco=300Mhz  Cpu(core)=100Mhz -> M=15   N=1 CPU div =3
Which configuration do you recommend. Having smaller M and N value or smaller crystal for EMC ?

lower value of Fcco result in lower power dissipation so should I always try to keep it low and it is the best configuration ?

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