can only read/write 64 byte to SDRAM

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can only read/write 64 byte to SDRAM

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Alex on Thu Oct 30 05:58:45 MST 2014
Hi,

I did a board design with a LPC1778 and an ISSI IS42S16100E SDRAM.
unfortunately I missed to connect the correct bank address line to the SDRAM. I connected P4.11 of the LPC to A11 of the SDRAM but as it is the bank address I should have connected P4.13 instead.

Currently I don't manage to get any data exchanged with the SDRAM. My question is if this is a result of the wrong bank address or if it is something else.

I would expect that at least one bank is working.

I attached a source file with my initialization code.

EDIT: My test code is able to write 64 byte to SDRAM and read it back. If I try to write more data, nothing is written. Does it only seem to be working due to buffering or is it working but there is a problem with row switching?

Thank you in advance.

kind regards
Alex

Original Attachment has been moved to: board_lowlevel.c.zip

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by dbtayl on Sat Nov 01 07:21:42 MST 2014
I should note that I really don't know what I'm talking about- I've never tried to use an external RAM module with a micro before, so I'm just throwing things out based on what I see in the datasheet.

My thoughts (see above if any of them are really dumb):

-You're observing the write-recovery period when trying to write to the RAM?

-The RAM specifies 200/166/143 MHz operation. I assume you're going slower than that. Is that a problem? Or that's just the max frequency, so anything under that is OK (probably the latter, but hey)?

-It looks like the RAS strobe has a higher latency than other timings- is that accounted for? Seems like it might jibe with the "64 bytes" part of your problem.

-Have you tried writing to a DIFFERENT 64-byte area of memory? Does that work OK?

-Can you re-write and re-read the same 64 bytes (eg, write 0x333333..., read it back, write 0x555555.... to the same location, read it back)?

-Are you sending the RAM commends to set the parameters you assume (and/or they match the defaults)? Things like burst length, CAS latency, etc.?


Hope something there helps! If it's not some stupid little mistake, I don't know if I can help any more than that- you'll need somebody that knows what they're doing.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Alex on Thu Oct 30 08:42:11 MST 2014
The Opcode is used only during the mode set command. I set the IOCON register for P4.11 to 0x28 to make sure that it is used as GPIO. Also is the pulldown enabled to make sure it has the correct level.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by dbtayl on Thu Oct 30 08:39:02 MST 2014
It says in the SDRAM datasheet of A11: "This signal becomes part of the OP CODE during mode register set command input."

Maybe that's part of your issue?
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