5V tolerant UART design question [SOLVED]

[lpcware]

Content originally posted in LPCWare by btix on Tue Apr 01 03:21:43 MST 2014
Hello everybody!
I'm pretty new here so I want to start greeting everybody and doing the compliments for the great forum, very helpful and informative.
Now, back to the topic.

I spent some time looking through the forum for the answer to an easy (hopefully not to dumb) question:
when, in the datasheet, it's said that a series of pin (in my case the one for UART0) is

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Quote:

5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL
levels and hysteresis.

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related to the pin P0[2] and P0[3], do that apply only when I use them like digital IO or that also menas that the UART interface itself is 5V tolerant provided the above conditions (the UART can be connected to a 5V UART external device) ?
Thanks in advance for the answer!
Best regards to everybody

[lpcware]

Content originally posted in LPCWare by btix on Thu Apr 03 23:46:16 MST 2014
Thanks you a lot again, your answer clared me from a lot of doubts.

I totally agree with you on every point.

I really appreciate your help.

Best regards,
Tiziano

[lpcware]

Content originally posted in LPCWare by lpcwizz on Thu Apr 03 11:33:51 MST 2014
there are 2 things to your prev post

1) the source follower (old days transistor emitter follower) implementation of the bss138 is a nice way to generically address the step-up issue, however it requires 3 parts resulting in board space, component insertion cost and additional possibilities of failures and it's detection over a single part solution ... only a thought.
the high level drive of a pullup increases the waste of current (power) in the low state over a push pull out stage of a dedicated buffer solution ...
also as you indicated, in the source follower implementation it's not really buffering, since the sink current will be carried through the part to gnd.
also the low level spec of the part pin still apply.

2) general rule for digital I/O pins ... as long as only digital peripherals use a pin, the digital specs of the pin apply, regardless of the digital peripheral selected ... the exceptions are analog I/O peripherals using a gpio pin, which have in most cases different specs, caused by switching or re-routing the pin to the analog peripheral ...
it doesn't really matter in the case of an analog peripheral being connected directly to the pin or the digital pin being disconnected or just being switched in parallel to the pin, if the, for example adc, can only handle the 3.3 V and the digital circuitry. the rule of the lowest (weakest) spec overrules the others

[lpcware]

Content originally posted in LPCWare by btix on Wed Apr 02 23:58:18 MST 2014
Thank you again for the links.
The logic levels that I need to interface are 3.3V and 5V. This is getting for me a "general question" on how it is better to interface 3.3V logic to 5V logic when using not the digital interface (which has been already asked on this forum many times) but more on how the inner peripherals can be handled in these cases.
I already considered that option and really that seem the way to go from the "safety" point of view.
What I was referring to with "the use of pass transistors with pull-ups" is what is used in some of the discrete components level converter that are proposed
online, like the one it is available form sparkfun (this is the link to the schematic of the product BOB-11978 from sparkfun, I don't post the link here since my previous attempt triggered the anti-spam filter and I suspect taht could be the issue ).
In that schematic the pull up are needed to make the actual logic high level to get to the right value, but obviously the devices must be able to drain the current that the pull-ups introduce while driving the signal low on the line.
My doubt is all about the ability for the LPC178X to be able to do that part of the work in a safe way since I found no exact data on the sinking current allowed for the peripheries.

Best regards
Tiziano

[lpcware]

Content originally posted in LPCWare by lpcwizz on Wed Apr 02 11:03:25 MST 2014
one option is also to use a CMOS Logic Level Shifter

http://www.ti.com/lit/ds/symlink/sn74lv1t34.pdf

or for multiple buffers

http://www.ti.com/logic/docs/translationresults.tsp?sectionId=458&voltageIn=3.3&searchDirection=1&vo...

if you specify your input criteria on this website it might eliminate some valuable choices like the xxHCT367/8 hex buffers if you need more than 1 or 2

basically if you select a xxHCTxx part you have TTL level input threshold levels 0.8 / 2.0 V which should work for 3.3 V cmos output drives.

i was once looking through some of the xCT datasheets and most of them defined cmos input levels ( 1/3 and 2/3 vdd) as their thresholds ... this was with ACT parts i believe, but this was a long while ago

without seeing your proposed circuit of "the use of pass transistors with pull-ups" it sounds like a signal inversion

[lpcware]

Content originally posted in LPCWare by btix on Tue Apr 01 23:43:36 MST 2014
Thanks for the answers, both of them are quite usefull indeed.
My main concern was about the safety on the receiving line, the adaptaion on the TX line is somenthing I already put inot acount from the beginning.
An easy way to handle the voltage level translations could be the use of pass transistors with pull-ups, but I?m not really sure that it's safe to consider the
output of the UART lines as open-drain could be safe, really I found nowhere such a statement so I think that could be too much of an assumption to make in this case.
Can anybody explain a bit more on the output stage that could be safe to consider for design?
Thanks again and best regards

Tiziano

[lpcware]

Content originally posted in LPCWare by rocketdawg on Tue Apr 01 11:44:24 MST 2014
probably not.  Although the input might tolerate a 5V signal and a resistor divider may lower that to a 3.3v level,
the output cannot generate a 5V signal.  it will generate something less the Vcc, typically < 3.3V.

the external UART at 5V might not consider 3.3 v as a logic high.  Only the external UART data sheet will confirm.

[lpcware]

Content originally posted in LPCWare by lpcwizz on Tue Apr 01 10:55:21 MST 2014
there are 2 answers to this question

1) as your quote says, if your chip has power applied, then the as "5 V tolerant" pins can have a signal level of 5 V applied to them, i.e. 5.0 V RxD signal.
if the chip is not powered, the signals on this pin is not supposed to exceed 3.6 V

basically, when the chip (board) is not powered, a 5 V signal from an external device (external board) connected to RxD would violate this spec

a simple R1 / R2 divider on the RxD input would solve the issue and a series resistor and clamping schottky diode to Vdd would prevent an accidental 5V coming in on the TxD pin exceeding the 3.6 V

(keep in mind that this series resistor / clamping diode has the potential to apply now a small current to the powered off Vdd rail)

2) in case of RS232 levels (up to +12 V / -12 V), all interface chips invert the Rx and Tx signals ... this is not directly related to 5 V tolerance, but good to know.