5V tolerant UART design question [SOLVED]

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by btix on Tue Apr 01 03:21:43 MST 2014
Hello everybody!
I'm pretty new here so I want to start greeting everybody and doing the compliments for the great forum, very helpful and informative.
Now, back to the topic.

I spent some time looking through the forum for the answer to an easy (hopefully not to dumb) question:
when, in the datasheet, it's said that a series of pin (in my case the one for UART0) is


5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL
levels and hysteresis.

related to the pin P0[2] and P0[3], do that apply only when I use them like digital IO or that also menas that the UART interface itself is 5V tolerant provided the above conditions (the UART can be connected to a 5V UART external device) ?
Thanks in advance for the answer!
Best regards to everybody