SPI Slave TX Underrun

[lpcware]

Content originally posted in LPCWare by jcc273 on Fri Jul 26 13:04:46 MST 2013
I figured this has to be documented somewhere but i can't seem to find it.  What exactly happens if i am running as an SPI Slave on the LPC1788 and my TX buffer is underrun?

By testing i think i have figured out what happens, but it is undesirable behavior.

What i am seeing in testing is this (SPI_MODE_1):

Master sends LPC a 5 Byte Message:  t,e,s,t,Line Break
During this transmission the LPC slave sends 0's
Master then clocks out 10 lines for the LPC to respond.  It is currently just reflecting so it sends t,e,s,t,Line Break back followed by 5 0's.

The process is then repeated, only the slave sends back:  t,e,s,t,Line Break,s,s,s,s,s
then the next time the slave sends data during the request: s,s,s,s,s
and again during the response:  t,e,s,t,Line Break,s,s,s,s,s

If i change the test string the result is different, so considering it is an 8-byte fifo it would appear that it wraps around and when the last byte is transmitted it automatically loads the next byte and keeps sending that until new data is written:

FIFO:  1   2   3   4   5   6    7   8
       t   e   s   t   _   ^/t  e   s
       t   _   ^/t e   s   t    _   ^/t
       e   s   t   _   ^/t...............

Where i put the arrows here is where it hits the end of the buffer and just seems to transmit whatever is in that position already, which is why i see s in all the blanks after a couple iterations.

What i would like to do is either:

A - Keep sending the last byte that was sent until new data is ready
or B - Disable sending any data until data is ready.

Now i see there is a Slave Data Disable that would appear to work for me.  Simply disable sending any data if there is none to send, HOWEVER, there is no interrupt for when the TX FIFO is empty, so i wouldn't know when to flag this disable : /. 

So any additional information that may help me would be greatly appreciated!  Right now the best thing i can think of is to keep putting data into the tx buffer when it is half empty to prevent the underrun altogether and i could just put 0's in if no data is ready, but that seems wasteful to me.

[lpcware]

Content originally posted in LPCWare by jcc273 on Fri Jul 26 14:51:20 MST 2013
So yeah im pretty sure what it does when underrun is after transmitting the last byte it progresses to the next position in the FIFO (Ring Buffer) and just keeps transmitting that until you right more data at which point it will process the byte you put into that position then move to the next one.

My solution was this:

When buffer is half empty interrupt:  if data left then put more data in and clear counter, else if counter > 1 then disable half empty interrupt, else stuff 0's and inc counter.

so that way before i stop filling the buffer i make sure it has been filled with 0s.  if i was to get more data along the way then when half empty it puts that instead and clears the counter.  So then when i am out of data it will be transmitting 0s always.  when i get more data i simply stuff the buffer then flip the interrupt back on and then since it is just waiting transmitting the same byte i have no delay before it starts transmitting my data.

This probably wouldn't have been such a mess if i was using conventional command response spi, but i wanted to be able to stream commands and just let the responses come as they may (I have an int line from slave that is pulled low when slave has data to send in case of no commands).

Good to go : ).