lpcware

INIT PLL problem in LPC1788FBD144

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by research on Tue Aug 07 21:41:29 MST 2012
Hi,

I am newbie in lpc1788. anybody can help me to  int PLL procedure for 64000 Clock in lpc1788 FBD144.


my code is

if ( LPC_SC->PLL0STAT & (1 << 25) )
{
// disconnect PLL0
//LPC_SC->PLL0CON &= ~0x02;
LPC_SC->PLL0CON =1;  /* Enable PLL, disconnected */
// feed
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
}
else
{

// disconnect PLL0
LPC_SC->PLL0CON &= ~0x02;
// feed
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
}
  // disable PLL0
  LPC_SC->PLL0CON = 0x00;
  // feed
  LPC_SC->PLL0FEED = 0xAA;
  LPC_SC->PLL0FEED = 0x55;



// enable main oscillator, 1MHz - 20MHz
  LPC_SC->SCS = 0x20;


  // wait until ready
  while (!(LPC_SC->SCS >> 6 & 0x1));




  // select main oscillator (12MHz) as input for PLL0
  LPC_SC->CLKSRCSEL = 0x01;

  // configure PLL0
  LPC_SC->PLL0CFG = (PLL_NSEL << 16) | PLL_MSEL;



  // feed
  LPC_SC->PLL0FEED = 0xAA;
  LPC_SC->PLL0FEED = 0x55;


  // enable PLL0
  LPC_SC->PLL0CON = 0x01;
  // feed
  LPC_SC->PLL0FEED = 0xAA;
  LPC_SC->PLL0FEED = 0x55;
Toggle_WD();

  // set CPU clock divider - CCLK = 64MHz
  LPC_SC->CCLKSEL = CCLK_DIV;


  // wait for lock
  while (!((LPC_SC->PLL0STAT >> 26) & 0x1)); // while ( ((LPC_SC->PLL0STAT & (1 << 26)) == 0) );/* Check lock bit status */



  // connect PLL0
  LPC_SC->PLL0CON = 0x03;
  // feed
  LPC_SC->PLL0FEED = 0xAA;
  LPC_SC->PLL0FEED = 0x55;

  Time(50);
// wait for connected
  while (!((LPC_SC->PLL0STAT >> 25) & 0x1));


while entering this routine, my hardware is restarted.

any body have idea..

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