lpcware

Sdram write issue

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Scieslik on Sun Apr 15 16:58:52 MST 2012
I am trying to connect some external SDRAM to the LPC1787 to use as a framebuffer source for an LCD screen.

I am using this SDRAM chip: IC42S16100E
Datasheet: http://www.issi.com/pdf/42S16100E.pdf

I have connected all the pins in accordance with the LPC1787 datasheet as follows:
<code>
LPC1787    |     IC42S16100E
----------------------------
A0         |     A0
A1         |     A1
A2         |     A2
A3         |     A3
A4         |     A4
A5         |     A5
A6         |     A6
A7         |     A7
A8         |     A8
A9         |     A9
A10        |     A10
A13 (Bank) |     A11 (Bank)
D0         |     D0
D1         |     D1
D2         |     D2
D3         |     D3
D4         |     D4
D5         |     D5
D6         |     D6
D7         |     D7
D8         |     D8
D9         |     D9
D10        |     D10
D11        |     D11
D12        |     D12
D13        |     D13
D14        |     D14
D15        |     D15
DQM0       |     UDQM
DQM1       |     LDQM
WE         |     WE
CAS        |     CAS
RAS        |     RAS
DYCS0      |     CS
CKE0       |     CKE
CLK0       |     CLK
</code>


Currently, I'm able to write 8 memory locations (32-bit format) consecutively with the project working as expected. When I try to clear the entire SDRAM location, the locations are just randomized.

I have tested as much hardware as I can, including the clock, clock enable, some data pins/address pins just to be sure that they are all functioning, and everything seems to be working. However, I can't clear the full SDRAM location.

Here is my initialization code for the SDRAM:

First the macros:
<code>
#define SDRAM_BASE_ADDR    (0xA0000000)    /* SDRAM Bank 0  */
#define SDRAM_SIZE         (0x200000)      /* 16Mbit Length */
</code>

Now the initialization:

<code>
void vd_g_IoSdramInitTask(void)
{
    uint32_t Temp;
    uint32_t u4_t_idx;
    uint32_t u4_t_tmp;
    volatile uint32_t *short_wr_ptr;

    /* Initialize EMC */
    EMC_Init();

    //Configure memory layout, but MUST DISABLE BUFFERs during configuration
    LPC_EMC->DynamicConfig0 = 0x00000080; /* 16Mbit, 1Mx16, 2 banks, row=11, column=8 */

    /*Configure timing for  ISSI SDRAM IC42S16100E */

    //Timing for 80MHz Bus
    LPC_EMC->DynamicRasCas0    = 0x00000303;     /* 3 RAS, 3 CAS latency */
    LPC_EMC->DynamicReadConfig = 0x00000001;     /* Command delayed strategy, using EMCCLKDELAY */
    LPC_EMC->DynamicRP         = 0x00000002;     /* ( n + 1 ) -> 3 clock cycles */
    LPC_EMC->DynamicRAS        = 0x00000005;     /* ( n + 1 ) -> 6 clock cycles */
    LPC_EMC->DynamicSREX       = 0x00000000;     /* ( n + 1 ) -> 1 clock cycles */
    LPC_EMC->DynamicAPR        = 0x00000004;     /* ( n + 1 ) -> 5 clock cycles */
    LPC_EMC->DynamicDAL        = 0x00000005;     /* ( n ) -> 5 clock cycles */
    LPC_EMC->DynamicWR         = 0x00000003;     /* ( n + 1 ) -> 4 clock cycles */
    LPC_EMC->DynamicRC         = 0x00000008;     /* ( n + 1 ) -> 9 clock cycles */
    LPC_EMC->DynamicRFC        = 0x00000008;     /* ( n + 1 ) -> 9 clock cycles */
    LPC_EMC->DynamicXSR        = 0x00000000;     /* ( n + 1 ) -> 1 clock cycles */
    LPC_EMC->DynamicRRD        = 0x00000001;     /* ( n + 1 ) -> 2 clock cycles */
    LPC_EMC->DynamicMRD        = 0x00000001;     /* ( n + 1 ) -> 2 clock cycles */


    for(u4_t_idx = (U4)0; u4_t_idx < 0x80; u4_t_idx++);    /* Wait 128 clock cycles */


    LPC_EMC->DynamicControl    = 0x00000103;     /* Issue PALL command */
    LPC_EMC->DynamicRefresh    = 0x00000002;     /* ( n * 16 ) -> 16 clock cycles */


    for(u4_t_idx = (U4)0; u4_t_idx < (U4)0x80; u4_t_idx++);        /* wait 128 AHB clock cycles */


    //Timing for 80MHz Bus
    LPC_EMC->DynamicRefresh    = 0x0000004E;         /* ( n * 16 ) -> 1248 clock cycles -> 15.6uS at 80MHz <= 15.625uS ( 32ms / 2048 row ) */


    for(u4_t_idx = (U4)0; u4_t_idx < (U4)0x00000080; u4_t_idx++);    /* wait 128 AHB clock cycles */

    LPC_EMC->DynamicControl    = 0x00000083;                         /* Issue MODE command */
    Temp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | 0xCC00));       /* Set the SDRAM Mode - 3 CAS, 8 Burst Length */


    for(u4_t_idx = (U4)0; u4_t_idx < (U4)0x00000080; u4_t_idx++);    /* wait 128 AHB clock cycles */


    //Timing for 80MHZ Bus
    LPC_EMC->DynamicControl    = 0x00000003;        /* Issue NORMAL command */

    //[re]enable buffers
    LPC_EMC->DynamicConfig0 |= 0x00080000;          /* 16Mbit, 1Mx16, 2 banks, row=11, column=8 */

    short_wr_ptr = (uint32_t *)SDRAM_BASE_ADDR;

    /* Memory Write Test */
    for (u4_t_idx = u4_t_tmp; u4_t_idx < SDRAM_SIZE/4; u4_t_idx++ )
    {
        *short_wr_ptr++ = (U4)0x0000AAAA;
        *short_wr_ptr++ = (U4)0x00005555;
    }
}
</code>

I have tried to write using "u4_t_idx < 8" , which managed to work. However, anything beyond that will not write to the SDRAM. In previous tests, the memory map looked like this:

(u4_t_idx < 8)
0xA0000000 :  AA AA 00 00 55 55 00 00 AA AA 00 00 55 55 00 00 AA AA 00 00 55 55 00 00 AA AA 00 00 55 55 00 00

(u4_t_idx < SDRAM_SIZE/4)
0xA0000000 :  CC 44 CC 44


So the memory is being set to random numbers when I try to write beyond 8 32-bit locations. Any suggestions to help fix this issue would be greatly appreciated.

Thanks in advance!

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