SSP in SPI slave mode: How to receive data without lag?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by MindBender on Wed Jul 29 00:00:59 MST 2015
We are using SSP0 in SPI slave mode and I notice our SPI received data handling is lagging behind on actual bus activity. I'm suspecting the FIFO is the culprit, because the two interrupts firing on received data, RXRIS en RTRIS, fire with a delay: The first after fires 32 bit times after the first byte at best, and the second fires after half the FIFO size bytes have been received. Or am I misunderstanding something?

If I'm correct, this would mean that the LPC slave SPI interface in unable to respond a master's command within a single SPI transaction.