lpcware

LPC1788 SDRAM timing problem

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by sebgonzo on Thu Jul 05 05:54:30 MST 2012
I'm making SDRAM layout for LPC1788. I want to do it right so I make timing budget calculations based on this article:

http://www.edn.com/design/test-and-measurement/4342433/Practical-timing-analysis-for-100-MHz-digital-designs

I think there are some errors in current datasheet (rev. 4 - May 2012) of LPC1788 (Table 18 on page 25):

th(Q) data output hold time   min. 0.2ns  max 1.6ns

If I understand it correctly this means, that data output is valid only for 0.2ns (worst case) after clock. My memory device, has minimum input hold time 0.8ns (and as I know most SDRAM's has similar value). Output hold time can't be lower than input hold time. I think this th(Q) is much to low.

I compared it with LPC1850 datasheet and in my opinion this is correct value (Table 23 on page 115):

th(Q) data output hold time   min. 0.5 × Tcy(clk) ns
where Tcy(clk) is clock period.

Also, I cant find any SDRAM layout guidelines for this microprocessor. I know there is Application Note for LPC32xx, but I can't find one for LPC1788.

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