Current on LPC1758

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Current on LPC1758

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Doron on Sun Jun 28 08:44:21 MST 2015
Hi,

In the data sheet it is written that the current is 7mA CCLK = 12 MHz; PLL disabled.

What is the CCLK ? and can i work with the internal clock of 4MHz when the PLL disabled ?

Thanks,

Doron
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Doron on Tue Jun 30 05:27:31 MST 2015
Hi,

We use the LPC1758FBD80 in our product and we have a problem with high current, Do you have any information like graph of core clock versus current consumtion ?

Thanks,

Doron
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by mc on Mon Jun 29 12:06:00 MST 2015
Hi Doron,
Please see comments below.

Quote:
In the data sheet it is written that the current is 7mA CCLK = 12 MHz; PLL disabled.



You can use 12MHz Crystal and do not enable PLL(see PLL0CON reg). Also used option /1 in CCLKCFG reg.


Quote:
What is the CCLK ?



It is Core clock frequency(Cortex M3 in this case).


Quote:
and can i work with the internal clock of 4MHz when the PLL disabled ?



Yes, you can use internal IRC which generates 4MHz Clock. Again set  PLL0CON and CCLKCFG.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Doron on Mon Jun 29 04:45:56 MST 2015
Hi Padjama,

Thanks, I search a graph the describe the current versus pll frequency.

Do you have any data ?

Thanks,

Doron
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by padmaja on Mon Jun 29 03:57:28 MST 2015

Hi doron,

              By using CPU clock divider (CLKCFG[7:0])option you can generate 4 MHZ cpu clock. Refer this           (http://www.nxp.com/documents/user_manual/UM10360.pdf) document for more details. :)

padmaja
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