Content originally posted in LPCWare by jborge on Mon Jul 27 10:49:57 MST 2015
lpc1788 208lqfp interfacing to IS42S32800D-7TL-TR SDRAM memory.
I have installed the IBIS models for the LPC1788 and the ISS SDRAM in ALTIUM designer for PCB waveform simulation..
When simulating I noticed the edge rates on the data lines from the SDRAM to the LPC1788 to be within reason for risetimes on the wave forms. I observe the expected overshoot, undershoot as I would expect to see.
When looking at waveforms for LPC1788 EMC pins, for example the CLK and DATA they seem to be heavily slewed.
So data wave forms going from the SDRAM to the LPC1788 have expected risetimes and data signals going from the LPC1788 to the SDRAM and heavily slewed waveforms.
There are several models:
for example:
out_2.5v_tp_out.mac
out_2.5v_st_out.mac
plus several more.
What IO model should I select for the CLK output, and memory outputs for the EMC pins?
Also I noticed that IBIS file for the LPC1788 does not load well into a text editor for viewing. It seem to be missing all the form feed and CR characters.
Where as the IBIS model for other components for example the lpc1850 and the SDRAM used above can easily be viewed and studied in a text editor.
Thanks in advance for any replies.
