lpcware

PWM

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by celephicus on Sun Oct 12 21:17:43 MST 2014
Can someone show me how to set up the SCT to generate PWM so that with zero in the relevant match register the output is permanently low, with half the value in match register 0 the duty is 50%, and with the match register 0 in the relevant match register the output is permanently high? I have tried the PWM example code from LPCOpen and numerour variations but I cannot seem to get rid of the 1 cycle high pulse when the counter resets, even with 0 in the match register.

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