PWM

[lpcware]

Content originally posted in LPCWare by celephicus on Sun Oct 12 21:17:43 MST 2014
Can someone show me how to set up the SCT to generate PWM so that with zero in the relevant match register the output is permanently low, with half the value in match register 0 the duty is 50%, and with the match register 0 in the relevant match register the output is permanently high? I have tried the PWM example code from LPCOpen and numerour variations but I cannot seem to get rid of the 1 cycle high pulse when the counter resets, even with 0 in the match register.

[lpcware]

Content originally posted in LPCWare by mc on Mon Oct 13 12:53:42 MST 2014
Hi celephicus,
To get low output, program duty cycle register with PWM period and clear output in conflict resolution register. 
To get high output, program duty cycle register with PWM period and set output in conflict resolution register.
This should give you low and high respectively on SCTimer/PWM outputs.

[lpcware]

Content originally posted in LPCWare by starblue on Mon Oct 13 09:27:41 MST 2014
Did you look at the SCT conflict resolution register?
You probably need to set it so that setting the output low takes precedence.

[lpcware]

Content originally posted in LPCWare by LabRat on Mon Oct 13 07:57:23 MST 2014
I'm not sure what you are trying to do...

You are switching PWM out pin with setting its match register to 0 / duty cycle / cycle time

and now you are surprised that switching isn't done before timer is reaching this match value?