ADC input structure

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by br1 on Tue Feb 16 03:21:40 MST 2016
Hi all,

I need the input structure and acquisition time of the 12 bit ADC on LPC1518 series.
The aim is to simulate the maximum source resistance (and sampling rate) I can connect to the ADC versus a tolerable offset error.

I use the ADC1_1 input in burst mode at maximum sampling rate (50MHz ADC clock).
I run a spice simulation with the data I found on the datasheet, or presumed, but it doesn't coincide with the prototype results.
Specifically I used:
* 0.32 pF ADC input capacitance (Cia) from Fig. 39 of datasheet
* 5 to 25 ohm multiplexer resistance (Rsw) from Fig. 39 of datasheet
* I assumed 13 cycles acquisition time and 12 cycles conversion time (user manual specify only 25 cycles overall)
* I assumed Cia charged to Vref or Vref/2 between every sample (because I saw a positive offset with a grounded input).
* I omitted Cdac from Fig. 39 of datasheet because not specified nor the other end connected

With the values as in the attached picture I get 8 mV of offset (from a grounded input) while actually I measured 60 mV.
It seems the Cia is an order of magnitude higher than what specified or Cdac influences the circuit.
What am I missing?