UART0 LSR self-clearing

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Scribe on Mon Jan 14 07:24:06 MST 2013
Hi guys,

I'm suffering from a little confusion. I'm banging a few bytes over to an LPC1227 running in 485 mode, they're reaching the FIFO buffer but at no stage is the RBR interrupt being triggered and, when I use Keil's Debug View to inspect UART0, the LSR appears to be clearing itself, even though it's not meant to clear until it has been read.

Other interrupts such as RX Line Interrupt appear to trigger just fine.

Any ideas?

Many thanks