lpcware

LPC1343 I2C master wrong frequency

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by an.kh. on Tue Jul 16 02:06:56 MST 2013
Hello!
I have found that I2C master clock frequency is slower than it must be.
For example, for 1 MHz clock it is needed to set divider to 72 MHz / 1 MHz = 72. With this setting, the resulting frequency is around 880 kHz. And so with 400 kHz... To set 1 MHz it is needed to set divider to 65 (h=33,l=32), for 400 kHz divider = 173 (h=87,l=86).

I am using standard startup files for 72 MHz with 12 MHz crystal and SSP port showing the correct calculated frequency, so main clock is indeed 72 MHz and the problem is with I2C only. Also I didn't find any errata regarding this problem. Does anyone know the origins of this problem and what can be done with it?

Outcomes