lpcware

UM10524 and LPCXpresso have incorrect/inconsistent documention for GPIO Pin Interrupt Select Register

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by mathseng on Fri Jul 17 00:40:35 MST 2015
UM10524 - LPC1315-16-17-45-46-47.pdf

Section: 3.5.30 GPIO Pin Interrupt Select register (PINTSEL0 to 7) (page 27/416)
a. Table 35 appears incorrect.
b. LPCXpresso Debug IDE display is inconsistent with entered data.

Documentation refers to pins 0..23 from port 0 and 24..55 from port 1
Actual setup is consistent with documentation from UM10462 3.5.33 Pin interrupt select registers (page 35/495)

I am unable to check PIO0.23 and PIO1.0, since I am using 33/48 pin devices, but programming these shows in the DebugIDE as 0/x17, 0/x18

Proven:
PIO0.2 shows as 0x02 in PINTSEL register, appears as Port 0, 0x02 in DebugIDE, and correctly operates as PIO0.2 in chip operation.
PIO1.26 shows as 0x32 in PINTSEL register, and appears as Port 1, 0x12 in DebugIDE
PIO1.20 shows as 0x2C in PINTSEL register, and appears as Port 1, 0x0c in DebugIDE, and correctly operates as PIO1.20 in chip operation

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