I am attempting to interface a MC9S12C128 controller (packaged on the CHIPS12 platform, by ElMicro) to a Maxim MAX3100 UART. It appears I am having timing issues with the MOSI and SCLK.
The 9S12 is the master, Mode 0, and the Maxim is the slave. The 9S12 is configured with automatic slave select. The SPI registers are configured as follows (16 Mhz oscillator on the 9S12)
SPIBR = 0x70
SPICR1 = 0xda
SPICR2 = 0x10
I am monitoring the SPI bus with a Lineeye protocol analyzer, a Total Phase SPI bus monitor (Beagle module), and an oscilloscope (monitoring all four lines). The data bits are sent by the 9S12, but neither the data analyzers nor the Max3100 correctly receives the data. The following two commands are sent:
0xc0, 0x2b (Write Maxim config reg)
0x40, 0x00 (read Maxim config reg).
The data analyzers report data, but the bits are incorrect. The oscilloscope shows the correct bit patterns sent, but the MOSI bits (transmitted) transition with the leading edge of the clock. According to the Maxim data sheet (and Maxim tech support verified) the MOSI bits must be set before the leading edge of the clock transitions.
I utilized a Total Phase SPI Master Mode development module (the Cheetah) and configured it as the master to the Maxim chip. With the Cheetah module, I can correctly transmit data. The scope shows the Cheetah module setting the MOSI bits before the leading clock edge.
I have successfully used the 9S12 SPI bus in the past, but in the prior application another 9S12 served as the slave module. The SPI ISR routines are the same for both the current and prior application. Anyone had similar experiences with the Maxim 3100? Any suggestions on how to correct the issue?