Setting Endpoint maxpacketsize for LPC11U37H

lpcware · ‎06-15-2016

Content originally posted in LPCWare by siangming on Thu Dec 11 19:11:09 MST 2014
Hi all,

I have a few questions for implementing USB on LPC11U37H and for USB in general..
Please bear with me..

1. Can i configure the LPC11U37H as a low-speed usb device instead of full-speed?
Firmware-wise, i have to configure the descriptors as per low-speed specs (example: Endpoint max packet size, etc...)
Hardware-wise, i have to put a pull-up resistor to the D- signal line. How about the USB clock?

2. On the topic of endpoint packet size... In the LPC11U37H, if i were to use it as full-speed, how do i configure the chip to set the endpoint max packet size? for example, in full-speed, the default control endpoint can have a maximum packet size of 8, 16, 32 or 64. (according to Jan Axelson, USB COMPLETE, fourth editon, chapter 3 page 68).
For LPC11U37, it is also stated in the manual (page 221, table 211) that "The packet size is configurable up to the maximum value shown in Table 211 for each type of end point."

Does it mean that the LPC11U37H can perform at various setting of different max packet size?

If so, do i have to specify to the chip to use which packet size setting?

if not, what max packet size will the chip use in the example of a full-speed control endpoint? And how will the chip know to limit its control endpoint max packet size to 8 in low-speed mode?

3. On the host side, i know we specify the endpoints max packet size in the descriptors (control EP packet size in device descriptor, other EP packet size in their respective endpoint descriptors). So these max packets sizes in the descriptors must tally with the settings in question 2 above?

Thank you so much for your patience...

lpcware · ‎06-15-2016

Content originally posted in LPCWare by mc on Thu Jan 15 19:58:55 MST 2015
Hi Tsuneo,
Thanks for your feedback. We will include your feedback in next UM/Datasheet release.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Tsuneo on Sat Dec 20 08:22:45 MST 2014

Quote:
The LPC11U37 can actually do low speed usb. You should set the USB clock to 6MHz.

Ah, thanks.
Please pass datasheet/user mannual update requests on this issue to appropriate department in NXP.
Otherwise, no one can imagine ;-)

My suggestion for update is,

A) UM10462: LPC11U3x/2x/1x User manual, Rev. 5.3 — 11 June 2014
http://www.nxp.com/documents/user_manual/UM10462.pdf

1) At the center of "Fig 7. LPC11U3x/2x/1x CGU block diagram" (p19)
USBUEN (USB clock update enable)
---->
USBCLKSEL/USBCLKUEN (USB clock update enable)

2) Also in the right side of the same Figure 7
USB 48 MHz CLOCK DIVIDER
---->
USB 48 or 6 MHz CLOCK DIVIDER

3) 3.5.22 USB clock source select register (p33)
The clock source can be either the USB PLL output or the main clock, and the clock can be further divided by the USBCLKDIV register (see Table 30) to obtain a 48 MHz clock.
---->
48 MHz (full-speed) or 6 MHz (low-speed)

4) 11.3 Features (p219)
- USB2.0 full-speed device controller.
---->
- USB2.0 full-speed and low-speed device controller.

5) 11.4 General description (p220)
The USB device controller on the LPC11U3x/2x/1x enables full-speed (12 Mb/s) data
exchange with a USB host controller.
---->
The USB device controller on the LPC11U3x/2x/1x enables full-speed (12 Mb/s) and low-speed (1.5 Mb/s) data exchange with a USB host controller.

6) 11.4.3 SoftConnect (p221)
The connection to the USB is accomplished by bringing USB_DP (for a full-speed device)
HIGH through a 1.5 kOhm pull-up resistor.
---->
Add this sentence after above one.
"For low-speed device, the pull-up resistor is attached to USB_MP."

7) 11.4.7 Clocking (p223)
USB main clock: The USB main clock is the 48 MHz +/- 500 ppm clock from the
dedicated USB PLL or the main clock (see Table 28).
---->
USB main clock: For full-speed mode, the USB main clock is the 48 MHz +/- 2,500 ppm clock from the dedicated USB PLL or the main clock (see Table 28).

For low-speed mode, the IRC is suitable as the clock source.
---->
For low-speed mode, the USB main clock is the 6 MHz +/- 15,000 ppm clock. The IRC is suitable as the clock source.

B) LPC11U3x datasheet, Rev. 2.2 — 11 March 2014
http://www.nxp.com/documents/data_sheet/LPC11U3X.pdf

1) 7.9 USB interface (p20)
The LPC11U3x USB interface consists of a full-speed device controller with on-chip PHY
(PHYsical layer) for device functions.
---->
The LPC11U3x USB interface consists of a full- and low-speed device controller with on-chip PHY
(PHYsical layer) for device functions.

2) 7.9.1.1 Features
- Fully compliant with USB 2.0 specification (full speed).
---->
- Fully compliant with USB 2.0 specification (full and low speed).

3) 11.1 Suggested USB interface solutions (p54)
These figures show just full-speed setup, ie. the pull-up resistor is attached to USB_DP side.
- Fig 27. USB interface on a self-powered device where USB_VBUS = 5 V
- Fig 28. USB interface on a bus-powered device

4) Add low-speed option (ie. pull-up on USB_MP) to these figures,
OR
Add a Remark, which tells "For low-speed setup, pull-up moves to USB_MP side"

Tsuneo

lpcware · ‎06-15-2016

Content originally posted in LPCWare by xianghuiwang on Fri Dec 19 17:51:31 MST 2014
Hi, Siangming/Tsuneo,

The LPC11U37 can actually do low speed usb. You should set the USB clock to 6MHz. The current ROM in LPC11U37 has the max packet size as hard coded at 64. But there can be a work around to change the packet size. We would publish the low speed usb examples with the lpcopen package in the near future.
Regards,

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Tsuneo on Fri Dec 12 10:26:39 MST 2014

Quote:
1. Can i configure the LPC11U37H as a low-speed usb device instead of full-speed?

You can’t.

11.3 Features
- USB2.0 full-speed device controller.

Also, there isn’t any bit on the USB registers, which switches into low-speed.

I suppose the original design of this SIE had both of full-/low-speed capability, but low-speed is dropped at actual implementation. The trace remains on the data sheet,

11.4.7 Clocking
- USB main clock: ... For low-speed mode, the IRC is suitable as the clock source.

Quote:
2. how do i configure the chip to set the endpoint max packet size?

This SIE hardware doesn’t concern to MPS (Max Packet Size), because it’s single transaction type. Your firmware should manage MPS.

- For OUT endpoints, your firmware passes a MPS buffer to the SIE. At OUT transaction, the SIE fills the buffer with incoming packet (MPS or less).
- For IN endpoints, your firmware passes a MPS (or less) packet to the SIE. And then, the SIE sends the packet to host at IN transaction.

In this way, SIE hardware works regardless of actual number of MPS.
That is, you may assign any number to MPS, as long as it satisfies USB2.0 spec.

Tsuneo