S12XDP512 pulse accumulator B missing control bits

[shedmeister]

The PBCTL register is missing a few of the control bits that PACTL has in the Enhanced Capture Timer. I can't find in the data sheet what mode it defaults to. Specifically, PAMOD (event counter or gated time accumulation), and PEDGE (which edge to trigger on). Thanks

[DPB]

Hello

Pulse Accumulator B operates in event counter mode (implied in figure 7-70)
EDG0B and EDG0A in TCTL4 determine the active edge for the 16-bit pulse accumulator PACB.

The documentation is indeed not very clear.
This shall be included on a list of improvements for future versions.

DPB