Spifi memory mapping shifted 1 byte???

[lpcware]

Content originally posted in LPCWare by diederikloos on Thu Dec 10 08:52:05 MST 2015
Setup:
LPC4357
custom board
eclipse, using arm-gcc-none-eabi
flash: S25FL512S
OS: ChibiOS

Hey guys,

I am trying to use the SPIFI library in combination with spansion S25FL512s flash memory. I managed to get the library working on LPC4357, but when i memory map the device, all the data I inserted seems to be shifted 1 byte to the left, even though I defined the base address as 0x14000000.
If I try to write 4 bytes, and then switch to memmapped mode, i can only see 3 bytes have been written. We tried to add 1 to the base addres, but then the last byte of the page (byte 512) will not be written. I've checked whether the buffers were 32 bit alligned (by (address & 0x03)). Does anyone have a clue why the memory mapping is shifted 1 byte?

[lpcware]

Content originally posted in LPCWare by mc on Fri Feb 12 12:46:32 MST 2016
Hi avenuti,
Thanks for bringing it up. We missed it. We had dummy code support in our old SPIFI library. It was an oversight.

[lpcware]

Content originally posted in LPCWare by avenuti on Fri Feb 12 11:22:15 MST 2016
I ran into this exact same problem two days ago, and also determined that the latency code was the issue (for once I actually should have checked this forum first - up until now it never has helped my specific problems). Good find!

@NXP: Why does the LPC SPIFI lib not control these latency codes for most of the flash chips it supports?

[lpcware]

Content originally posted in LPCWare by lintovincent88 on Thu Feb 11 03:06:02 MST 2016
Thank you for sharing...

by
Linto vincent

[lpcware]

Content originally posted in LPCWare by MikeSimmonds on Sat Dec 12 09:14:58 MST 2015
Thank you for sharing!
There is too much 'hit and run' sometimes.

Cheers, Mike.

[lpcware]

Content originally posted in LPCWare by diederikloos on Sat Dec 12 02:17:22 MST 2015
I found the solution for this problem. It has to do with S25Fl512S.

I found that toggling quad mode caused the bytes to shift as well. Then i started looking at the datasheets more thoroughly, and i found that there are latency codes included (latency codes depict how many dummy cycles there are between the address and the actual data during a read command). Basically, what happened was that the writing to flash succeeded, but when reading, there were one or multiple dummy cycles included, causing the data to shift 1 byte. In the spifilib, there is another spansion chip mentioned, where the latency bits are set to zero when initializing the device. By writing 2 zero's to the 14th and 15th bit of the status register, i disabled this latency mode, and suddenly the memory was alligned again. Hope this helps anyone else who might have the same problem in the future.

[lpcware]

Content originally posted in LPCWare by diederikloos on Fri Dec 11 02:20:34 MST 2015
Yesterday, I saw this post about the reset boolean parameter that is part of the spifiInit function.
This morning I've set this boolean to false, and suddenly the memory mapping is alligned properly. I will try to troubleshoot this further, but so far, it seems that resetting the spifi controller causes this weird bug.